1990/0825/power/main.c (diff list | history)

1990/0802/sys/src/9/power/main.c:133,142 – 1990/0825/sys/src/9/power/main.c:133,143 (short | long | prev | next)
1990/0227		/* * Tell CPU 0's SBCC to map all interrupts from the IO2 to MIPS level 5 * * Since there are 6 MIPS hardware interrupts and the SBCC can generate * only 5, one hardware interrupt can't be generated by the SBCC. SBCC * interrupt 4 maps to MIPS interrupt 5, SBCC interrupt 0 maps to MIPS * interrupt 0. I don't know which interrupt is missing. -- presotto
1990/0825		* 0x01 level 0 * 0x02 level 1 * 0x04 level 2 * 0x08 level 4 * 0x10 level 5
1990/0227		*/ SBCCREG->flevel = 0x10;