1990/0907/power/main.c (diff list | history)

1990/09051/sys/src/9/power/main.c:35,51 – 1990/0907/sys/src/9/power/main.c:35,47 (short | long | prev | next)
1990/0504		char sysname[64];
1990/0826		/*
1990/0905		* IO board type, number of interrupt levels, and interrupt enable mask
1990/0907		* IO board type
1990/0826		*/ int ioid;
1990/0905		int iolevels; int iomask;
1990/0826
1990/0227		void main(void) {
1990/0424		int i;
1990/0801		machinit();
1990/0227		active.exiting = 0; active.machs = 1;
1990/09051/sys/src/9/power/main.c:61,73 – 1990/0907/sys/src/9/power/main.c:57,68
1990/0227		clockinit(); alarminit();
1990/0826		ioboardinit();
1990/0907		ioboardid();
1990/0227		chandevreset();
1990/09051		sinit();
1990/0227		streaminit();
1990/0718		sysloginit();
1990/0227		pageinit(); userinit();
1990/0826		ioboardid();
1990/0227		launchinit(); schedinit(); }
1990/09051/sys/src/9/power/main.c:114,129 – 1990/0907/sys/src/9/power/main.c:109,124
1990/0826		{ switch(ioid){ case IO2R1: print("IO2 revision 1\n");
1990/0907		iprint("IO2 revision 1\n");
1990/0826		break; case IO2R2: print("IO2 revision 2\n");
1990/0907		iprint("IO2 revision 2\n");
1990/0826		break; case IO3R1: print("IO3 revision 1\n");
1990/0907		iprint("IO3 revision 1\n");
1990/0826		break; default: print("unknown IO board\n");
1990/0907		iprint("unknown IO board\n");
1990/0826		break; } }
1990/09051/sys/src/9/power/main.c:136,166 – 1990/0907/sys/src/9/power/main.c:131,146
1990/0826		ioboardinit(void)
1990/0227		{ long i;
1990/0905		int intrs;
1990/0826
1990/0905		/* * set up interrupts based on IO board type */
1990/0826		ioid = *IOID;
1990/0905		switch(ioid){ case IO2R1: case IO2R2: iolevels = 8; iomask = 0xff; break; case IO3R1: iolevels = 11; iomask = 0x7fe; break; }
1990/0227		/* * reset VME bus (MODEREG is on the IO2) */ MODEREG->resetforce = (1<<1);
1990/0907		MODEREG->resetforce = (1<<1) | (1<<0);
1990/0227		for(i=0; i<1000000; i++) ; MODEREG->resetforce = 0;
1990/0907		MODEREG->resetforce = (1<<0);
1990/0227		MODEREG->masterslave = (SLAVE<<4) | MASTER; /*
1990/09051/sys/src/9/power/main.c:170,178 – 1990/0907/sys/src/9/power/main.c:150,158
1990/0227		setvmevec(i, novme); /*
1990/0905		* tell IO2 to send all interrupts to CPU 0's SBCC
1990/0907		* tell IO2 to sent all interrupts to CPU 0's SBCC
1990/0227		*/
1990/0905		for(i=0; i<iolevels; i++)
1990/0907		for(i=0; i<8; i++)
1990/0227		INTVECREG->i[i].vec = 0<<8; /*
1990/09051/sys/src/9/power/main.c:192,204 – 1990/0907/sys/src/9/power/main.c:172,184
1990/0227		* The SBCC 16 bit registers are read/written as ulong, but only * bits 23-16 and 7-0 are meaningful. */
1990/0905		SBCCREG->fintenable |= iomask; /* turn on all interrupts */
1990/0907		SBCCREG->fintenable |= 0xff; /* allow all interrupts on the IO2 */
1990/0227		SBCCREG->idintenable |= 0x800000; /* allow interrupts from the IO2 */ /* * enable all interrupts on the IO2 */
1990/0905		*IO2SETMASK = iomask;
1990/0907		*IO2SETMASK = 0xff;
1990/0227		} void
1990/09051/sys/src/9/power/main.c:607,612 – 1990/0907/sys/src/9/power/main.c:587,597
1990/0614		conf.npage = conf.npage0;
1990/0504		/*
1990/0907		* clear MP bus error caused by sizing memory */ i = *SBEADDR; /*
1990/0504		* set minimal default values */ conf.nmach = 1;
1990/09051/sys/src/9/power/main.c:629,634 – 1990/0907/sys/src/9/power/main.c:614,622
1990/0424		conf.npte = 4 * conf.npage;
1990/0227		conf.nqueue = 5 * conf.nstream; conf.nblock = 16 * conf.nstream;
1990/0907		conf.nnoifc = 1; conf.nnoconv = 32; conf.nurp = 256;
1990/0430
1990/0504		confread();