plan 9 kernel history: overview | file list | diff list

1990/0907/power/trap.c (diff list | history)

1990/0905/sys/src/9/power/trap.c:180,1931990/0907/sys/src/9/power/trap.c:180,185 (short | long | prev | next)
1990/0227    
} 
 
void 
1990/0905    
mpbuserror(void) 
{ 
	print("io2 mp bus error %d %lux %lux\n", 0, 
		*MPBERR0, *MPBERR1); 
	*MPBERR0 = 0; 
} 
                 
void 
1990/0731    
intr(ulong cause, ulong pc) 
1990/0227    
{ 
	int i, pend; 
1990/0905/sys/src/9/power/trap.c:205,2111990/0907/sys/src/9/power/trap.c:197,203
1990/0227    
	if(cause & INTR5){ 
 
		if(!(*MPBERR1 & (1<<8))){ 
1990/0830    
			print("MP bus error %lux %lux\n", *MPBERR0, *MPBERR1); /**/ 
1990/0907    
			iprint("MP bus error %lux %lux\n", *MPBERR0, *MPBERR1); /**/ 
1990/0227    
			*MPBERR0 = 0; 
			i = *SBEADDR; 
		} 
1990/0905/sys/src/9/power/trap.c:235,2691990/0907/sys/src/9/power/trap.c:227,260
1990/0227    
		/* 
		 *  5a. process lance, scsi 
		 */ 
1990/0907    
	loop: 
1990/0227    
		if(pend & 1) { 
			v = INTVECREG->i[0].vec; 
1990/0905    
			if(!(v & (1<<12))) 
				mpbuserror(); 
			if(!(v & (1<<2))) 
				lanceintr(); 
			if(!(v & (1<<1))) 
				lanceparity(); 
			if(!(v & (1<<0))) 
				print("SCSI interrupt\n"); 
1990/0907    
			if(!(v & (1<<12))){ 
				print("io2 mp bus error %d %lux %lux\n", 0, 
					*MPBERR0, *MPBERR1); 
				*MPBERR0 = 0; 
			} 
			switch(ioid){ 
			case IO2R1: 
			case IO2R2: 
				if(!(v & (1<<2))) 
					lanceintr(); 
				if(!(v & (1<<1))) 
					lanceparity(); 
				if(!(v & (1<<0))) 
					print("SCSI interrupt\n"); 
				break; 
			case IO3R1: 
				if(v & (1<<2)) 
					lance3intr(); 
				if(v & (1<<1)) 
					print("SCSI 1 interrupt\n"); 
				if(v & (1<<0)) 
					print("SCSI 0 interrupt\n"); 
				break; 
			} 
1990/0227    
		} 
1990/0905    
		if(pend & (1<<10)) { 
			v = INTVECREG->i[10].vec; 
			if(!(v & (1<<12))) 
				mpbuserror(); 
			lance3intr(); 
		} 
		if(pend & (1<<8)) { 
			v = INTVECREG->i[10].vec; 
			if(!(v & (1<<12))) 
				mpbuserror(); 
			print("SCSI0 interrupt\n"); 
		} 
		if(pend & (1<<9)) { 
			v = INTVECREG->i[10].vec; 
			if(!(v & (1<<12))) 
				mpbuserror(); 
			print("SCSI1 interrupt\n"); 
		} 
1990/0227    
		/* 
		 *  5b. process vme 
		 *  i bet i can guess your level 
1990/0905/sys/src/9/power/trap.c:272,2791990/0907/sys/src/9/power/trap.c:263,273
1990/0227    
		for(i=1; pend; i++) { 
			if(pend & 1) { 
				v = INTVECREG->i[i].vec; 
1990/0905    
				if(!(v & (1<<12))) 
					mpbuserror(); 
1990/0907    
				if(!(v & (1<<12))){ 
					print("io2 mp bus error %d %lux %lux\n", i, 
						*MPBERR0, *MPBERR1); 
					*MPBERR0 = 0; 
				} 
1990/0227    
				v &= 0xff; 
				(*vmevec[v])(v); 
			} 
1990/0905/sys/src/9/power/trap.c:282,2881990/0907/sys/src/9/power/trap.c:276,282
1990/0227    
		/* 
		 *  6. re-enable interrupts 
		 */ 
1990/0905    
		*IO2SETMASK = iomask; 
1990/0907    
		*IO2SETMASK = 0xff; 
1990/0227    
		cause &= ~INTR5; 
	} 
	if(cause) 


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comments to russ cox (rsc@swtch.com)