1991/0703/pc/io.h (diff list | history)

1991/0703/sys/src/9/pc/io.h:1,20 – 1991/0704/sys/src/9/pc/io.h:1,50 (short | long | prev | next)
1991/0703		/* * interrupt levels
1991/0704		* 8259 interrupt controllers
1991/0703		*/ enum { Clockvec= 8, Kbdvec= 9, Floppyvec= 14,
1991/0704		enum { Int0ctl= 0x20, /* control port */ Int0aux= 0x21, /* everything else port */ Int1ctl= 0xA0, /* control port */ Int1aux= 0xA1, /* everything else port */ Intena= 0x20, /* written to Intctlport, enables next int */ Int0vec= 17, /* first interrupt vector used by the 8259 */ Clockvec= Int0vec+0, /* clock interrupts */ Kbdvec= Int0vec+1, /* keyboard interrupts */
1991/0703		};
1991/0704		#define INT0ENABLE outb(Int0ctl, Intena) #define INT1ENABLE outb(Int1ctl, Intena)
1991/0703		/* * damned 8259, assume DOS sets it up for us
1991/0704		* 8253 timer
1991/0703		*/ enum { Intctlport= 0x20, /* 8259 control port */ Intctlmask= 0x21, /* interrupt mask */
1991/0704		enum { Timerctl= 0x43, /* control port */ Timercnt= 0x40, /* timer count port (outb count-1) */ Timericnt= 0x41, /* timer count input port */
1991/0703		Intenable= 0x20, /* written to Intctlport, enables next int */
1991/0704		Timerlatch= 0x40, /* latch count into Timericnt */
1991/0703		}; #define INTENABLE outb(Intctlport, Intenable)
1991/0704		/* * 8237 dma controllers */ enum { /* * the byte registers for DMA0 are all one byte apart */ Dma0= 0x00, Dma0status= Dma0+0x8, /* status port */ Dma0reset= Dma0+0xD, /* reset port */ /* * the byte registers for DMA1 are all two bytes apart (why?) */ Dma1= 0xC0, Dma1status= Dma1+2*0x8, /* status port */ Dma0reset= Dma1+2*0xD, /* reset port */ };