1991/0706/pc/trap.c (diff list | history)

pc/trap.c on 1991/0613
1991/0613		#include "u.h" #include "lib.h" #include "mem.h" #include "dat.h" #include "fns.h" #include "io.h"
1991/0703		#include "ureg.h"
1991/0613		/*
1991/0614		* trap/interrupt gates
1991/0613		*/
1991/0703		Segdesc ilt[256]; void (*ivec[256])(void*); void sethvec(int v, void (*r)(void), int type)
1991/0613		{
1991/0703		ilt[v].d0 = ((ulong)r)&0xFFFF|(KESEL<<16); ilt[v].d1 = ((ulong)r)&0xFFFF0000|SEGP|SEGPL(3)|type; }
1991/0614
1991/0703		void
1991/0706		setvec(int v, void (*r)(Ureg*), int type)
1991/0703		{ ilt[v].d1 &= ~SEGTYPE; ilt[v].d1 |= type; ivec[v] = r; }
1991/0614		/*
1991/0703		* set up the interrupt/trap gates
1991/0614		*/
1991/0703		void trapinit(void) { int i;
1991/0614
1991/0703		/* * set the standard traps */ sethvec(0, intr0, SEGTG); sethvec(1, intr1, SEGTG); sethvec(2, intr2, SEGTG); sethvec(3, intr3, SEGTG); sethvec(4, intr4, SEGTG); sethvec(5, intr5, SEGTG); sethvec(6, intr6, SEGTG); sethvec(7, intr7, SEGTG); sethvec(8, intr8, SEGTG); sethvec(9, intr9, SEGTG); sethvec(10, intr10, SEGTG); sethvec(11, intr11, SEGTG); sethvec(12, intr12, SEGTG); sethvec(13, intr13, SEGTG); sethvec(14, intr14, SEGTG); sethvec(15, intr15, SEGTG); sethvec(16, intr16, SEGTG);
1991/0706		sethvec(17, intr17, SEGTG); sethvec(18, intr18, SEGTG); sethvec(19, intr19, SEGTG); sethvec(20, intr20, SEGTG); sethvec(21, intr21, SEGTG); sethvec(22, intr22, SEGTG); sethvec(23, intr23, SEGTG);
1991/0703		/* * set all others to unknown */
1991/0706		for(i = 24; i < 256; i++)
1991/0703		sethvec(i, intrbad, SEGIG); /* * tell the hardware where the table is (and how long) */ lidt(ilt, sizeof(ilt));
1991/0704		/* * Set up the 8259 interrupt processor #1. * Make 8259 interrupts starting at vector I8259vec. * * N.B. This is all magic to me. It comes from the * IBM technical reference manual. I just * changed the vector. */
1991/0705		outb(Int0ctl, 0x11); /* ICW1 - edge, master, ICW4 */ outb(Int0aux, Int0vec); /* ICW2 - interrupt vector */ outb(Int0aux, 0x04); /* ICW3 - master level 2 */ outb(Int0aux, 0x01); /* ICW4 - master, 8086 mode */ outb(Int0aux, 0x00); /* mask - all enabled */
1991/0703		}
1991/0614		/*
1991/0703		* All traps
1991/0614		*/
1991/0703		trap(Ureg *ur)
1991/0614		{
1991/0703		if(ur->trap>=256 || ivec[ur->trap] == 0) panic("bad trap type %d\n", ur->trap); (*ivec[ur->trap])(ur);
1991/0706		INT0ENABLE;
1991/0614		}