| plan 9 kernel history: overview | file list | diff list |
1991/0731/pc/trap.c (diff list | history)
| 1991/0727/sys/src/9/pc/trap.c:10,15 – 1991/0731/sys/src/9/pc/trap.c:10,26 (short | long | prev | next) | ||
| 1991/0720 | void noted(Ureg*, ulong); void notify(Ureg*); | |
| 1991/0731 | void intr0(void), intr1(void), intr2(void), intr3(void); void intr4(void), intr5(void), intr6(void), intr7(void); void intr8(void), intr9(void), intr10(void), intr11(void); void intr12(void), intr13(void), intr14(void), intr15(void); void intr16(void), intr17(void), intr18(void), intr19(void); void intr20(void), intr21(void), intr22(void), intr23(void); void intr24(void), intr25(void), intr26(void), intr27(void); void intr28(void), intr29(void), intr30(void), intr31(void); void intr64(void); void intrbad(void); | |
| 1991/0613 | /* | |
| 1991/0709 | * 8259 interrupt controllers */ | |
| 1991/0727/sys/src/9/pc/trap.c:23,30 – 1991/0731/sys/src/9/pc/trap.c:34,41 | ||
| 1991/0709 | EOI= 0x20, /* non-specific end of interrupt */ }; | |
| 1991/0731 | int int0mask = 0xff; /* interrupts enabled for first 8259 */ int int1mask = 0xff; /* interrupts enabled for second 8259 */ | |
| 1991/0709 | /* | |
| 1991/0614 | * trap/interrupt gates | |
| 1991/0727/sys/src/9/pc/trap.c:50,55 – 1991/0731/sys/src/9/pc/trap.c:61,69 | ||
| 1991/0709 | if((v&~0x7) == Int0vec){ int0mask &= ~(1<<(v&7)); outb(Int0aux, int0mask); | |
| 1991/0731 | } else if((v&~0x7) == Int1vec){ int1mask &= ~(1<<(v&7)); outb(Int1aux, int1mask); | |
| 1991/0709 | } | |
| 1991/0703 | } | |
| 1991/0727/sys/src/9/pc/trap.c:62,67 – 1991/0731/sys/src/9/pc/trap.c:76,87 | ||
| 1991/0703 | int i; | |
| 1991/0614 | ||
| 1991/0703 | /* | |
| 1991/0731 | * set all interrupts to panics */ for(i = 32; i < 256; i++) sethvec(i, intrbad, SEGIG, 0); /* | |
| 1991/0703 | * set the standard traps */ | |
| 1991/0719 | sethvec(0, intr0, SEGIG, 0); | |
| 1991/0727/sys/src/9/pc/trap.c:80,85 – 1991/0731/sys/src/9/pc/trap.c:100,109 | ||
| 1991/0719 | sethvec(13, intr13, SEGIG, 0); sethvec(14, intr14, SEGIG, 0); sethvec(15, intr15, SEGIG, 0); | |
| 1991/0731 | /* * set the standard devices */ | |
| 1991/0719 | sethvec(16, intr16, SEGIG, 0); sethvec(17, intr17, SEGIG, 0); sethvec(18, intr18, SEGIG, 0); | |
| 1991/0727/sys/src/9/pc/trap.c:88,101 – 1991/0731/sys/src/9/pc/trap.c:112,127 | ||
| 1991/0719 | sethvec(21, intr21, SEGIG, 0); sethvec(22, intr22, SEGIG, 0); sethvec(23, intr23, SEGIG, 0); | |
| 1991/0731 | sethvec(24, intr24, SEGIG, 0); sethvec(25, intr25, SEGIG, 0); sethvec(26, intr26, SEGIG, 0); sethvec(27, intr27, SEGIG, 0); sethvec(28, intr28, SEGIG, 0); sethvec(29, intr29, SEGIG, 0); sethvec(30, intr30, SEGIG, 0); sethvec(31, intr31, SEGIG, 0); | |
| 1991/0703 | /* | |
| 1991/0718 |
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| 1991/0703 |
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| 1991/0706 |
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| 1991/0710 |
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| 1991/0703 |
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| 1991/0710 | * system calls */ sethvec(64, intr64, SEGTG, 3); | |
| 1991/0727/sys/src/9/pc/trap.c:115,122 – 1991/0731/sys/src/9/pc/trap.c:141,166 | ||
| 1991/0709 | outb(Int0ctl, 0x11); /* ICW1 - edge triggered, master, ICW4 will be sent */ outb(Int0aux, Int0vec); /* ICW2 - interrupt vector offset */ | |
| 1991/0705 |
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| 1991/0731 | outb(Int0aux, 0x04); /* ICW3 - have slave on level 2 */ | |
| 1991/0709 | outb(Int0aux, 0x01); /* ICW4 - 8086 mode, not buffered */ | |
| 1991/0731 | /* * Set up the second 8259 interrupt processor. * Make 8259 interrupts start at CPU vector Int0vec. * Set the 8259 as master with edge triggered * input with fully nested interrupts. */ outb(Int1ctl, 0x11); /* ICW1 - edge triggered, master, ICW4 will be sent */ outb(Int1aux, Int1vec); /* ICW2 - interrupt vector offset */ outb(Int1aux, 0x02); /* ICW3 - I am a slave on level 2 */ outb(Int1aux, 0x01); /* ICW4 - 8086 mode, not buffered */ /* * pass #2 8259 interrupts to #1 */ int0mask &= ~0x04; outb(Int0aux, int0mask); | |
| 1991/0703 | } | |
| 1991/0614 | /* | |
| 1991/0727/sys/src/9/pc/trap.c:125,143 – 1991/0731/sys/src/9/pc/trap.c:169,196 | ||
| 1991/0710 | void | |
| 1991/0703 | trap(Ureg *ur) | |
| 1991/0614 | { | |
| 1991/0703 |
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| 1991/0711 |
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| 1991/0731 | int v; int c; | |
| 1991/0703 | ||
| 1991/0731 | v = ur->trap; if(v>=256 || ivec[v] == 0) panic("bad trap type %d %lux\n", v, ur->pc); | |
| 1991/0709 | /* * call the trap routine */ | |
| 1991/0703 |
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| 1991/0731 | (*ivec[v])(ur); | |
| 1991/0709 | /* * tell the 8259 that we're done with the * highest level interrupt */ | |
| 1991/0731 | c = v&~0x7; if(c==Int0vec || c==Int1vec){ outb(Int0ctl, EOI); if(c == Int1vec) outb(Int1ctl, EOI); } | |
| 1991/0710 | } /* | |
| 1991/0727/sys/src/9/pc/trap.c:173,220 – 1991/0731/sys/src/9/pc/trap.c:226,232 | ||
| 1991/0718 | /* | |
| 1991/0710 | * system calls */ | |
| 1991/0720 |
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| 1991/0731 | #include "../port/systab.h" | |
| 1991/0720 | ||
| 1991/0710 | long syscall(Ureg *ur) | |