1991/0804/pc/devuart.c (diff list | history)

1991/0803/sys/src/9/pc/devuart.c:49,55 – 1991/0804/sys/src/9/pc/devuart.c:49,55 (short | long | prev | next)
1991/0801		{ QLock; int port; ushort sticky[16]; /* sticky write register values */
1991/0804		uchar sticky[8]; /* sticky write register values */
1991/0801		int printing; /* true if printing */ /* console interface */
1991/0803/sys/src/9/pc/devuart.c:70,77 – 1991/0804/sys/src/9/pc/devuart.c:70,77
1991/0801		#define UartFREQ 1846200 #define uartwrreg(u,r,v) outb(u->port + r, u->sticky[r] | v) #define uartrdreg(u,r) inb(u->port + r)
1991/0804		#define uartwrreg(u,r,v) outb((u)->port + r, (u)->sticky[r] | (v)) #define uartrdreg(u,r) inb((u)->port + r)
1991/0801		void uartintr(Uart*); void uartintr0(Ureg*);
1991/0803/sys/src/9/pc/devuart.c:91,98 – 1991/0804/sys/src/9/pc/devuart.c:91,98
1991/0803		brconst = (UartFREQ+8*rate-1)/(16*rate);
1991/0801		uartwrreg(up, Format, Dra); uartwrreg(up, Dmsb, (brconst>>8) & 0xff); uartwrreg(up, Dlsb, brconst & 0xff);
1991/0804		outb(up->port+Dmsb, (brconst>>8) & 0xff); outb(up->port+Dlsb, brconst & 0xff);
1991/0801		uartwrreg(up, Format, 0); }
1991/0803/sys/src/9/pc/devuart.c:148,154 – 1991/0804/sys/src/9/pc/devuart.c:148,154
1991/0801		already = 1; /* * get port addresses
1991/0804		* set port addresses
1991/0801		*/ uart[0].port = 0x3F8; uart[1].port = 0x2F8;