1991/0809/pc/main.c (diff list | history)

1991/0808/sys/src/9/pc/main.c:28,36 – 1991/0809/sys/src/9/pc/main.c:28,34 (short | long | prev | next)
1991/0716		grpinit(); chaninit();
1991/0711		alarminit();
1991/0801		print("chandevreset\n"); delay(1000);
1991/0716		chandevreset();
1991/0801		print("streaminit\n"); delay(1000);
1991/0716		streaminit(); swapinit(); pageinit();
1991/0808/sys/src/9/pc/main.c:218,223 – 1991/0809/sys/src/9/pc/main.c:216,223
1991/0711		conf.arp = 32; conf.frag = 32; conf.cntrlp = 0;
1991/0809		conf.nfloppy = 1; conf.nhard = 1;
1991/0711		}
1991/0716		/*
1991/0808/sys/src/9/pc/main.c:346,368 – 1991/0809/sys/src/9/pc/main.c:346,379
1991/0803		/* * set a bit in the PMU */
1991/0809		Lock pmulock;
1991/0803		int pmuwrbit(int index, int bit, int pos) {
1991/0809		lock(&pmulock);
1991/0803		outb(Pmucsr, 0x02); /* next is command request */ if(pmuready() < 0)
1991/0809		if(pmuready() < 0){ unlock(&pmulock);
1991/0803		return -1;
1991/0809		}
1991/0803		outb(Pmudata, (2<<4) | index); /* send write bit command */ outb(Pmucsr, 0x01); /* send available */ if(pmubusy() < 0)
1991/0809		if(pmubusy() < 0){ unlock(&pmulock);
1991/0803		return -1;
1991/0809		}
1991/0803		outb(Pmucsr, 0x01); /* next is data */ if(pmuready() < 0)
1991/0809		if(pmuready() < 0){ unlock(&pmulock);
1991/0803		return -1;
1991/0809		}
1991/0803		outb(Pmudata, (bit<<3) | pos); /* send bit to write */ outb(Pmucsr, 0x01); /* send available */ if(pmubusy() < 0)
1991/0809		if(pmubusy() < 0){ unlock(&pmulock);
1991/0803		return -1;
1991/0809		} unlock(&pmulock);
1991/0803		} /*