1991/0810/pc/devuart.c (diff list | history)

1991/0808/sys/src/9/pc/devuart.c:32,38 – 1991/0810/sys/src/9/pc/devuart.c:32,38 (short | long | prev | next)
1991/0801		Dtr= (1<<0), /* data terminal ready */ Rts= (1<<1), /* request to send */ Ri= (1<<2), /* ring */ Dcd= (1<<3), /* carrier */
1991/0810		Inton= (1<<3), /* turn on interrupts */
1991/0801		Loop= (1<<4), /* loop bask */ Lstat= 5, /* line status */ Inready=(1<<0), /* receive buffer full */
1991/0808/sys/src/9/pc/devuart.c:164,173 – 1991/0810/sys/src/9/pc/devuart.c:164,176
1991/0801		* set rate to 9600 baud. * 8 bits/character. * 1 stop bit.
1991/0810		* interrupts enabled.
1991/0801		*/ uartsetbaud(up, 9600); up->sticky[Format] = Bits8; uartwrreg(up, Format, 0);
1991/0810		up->sticky[Mctl] |= Inton; uartwrreg(up, Mctl, 0x0);
1991/0801		} }
1991/0808/sys/src/9/pc/devuart.c:209,256 – 1991/0810/sys/src/9/pc/devuart.c:212,269
1991/0801		IOQ *cq;
1991/0806		int s, l;
1991/0801
1991/0806		l = uartrdreg(up, Lstat);
1991/0803		s = uartrdreg(up, Istat);
1991/0806		cq = up->iq; while(l & Inready){ ch = uartrdreg(up, Data) & 0xff; if(cq->putc) (*cq->putc)(cq, ch); else { putc(cq, ch); if(up->delim[ch/8] & (1<<(ch&7)) )
1991/0810		for(;;){ s = uartrdreg(up, Istat); switch(s){ case 6: /* receiver line status */ l = uartrdreg(up, Lstat); break; case 4: /* received data available */ cq = up->iq; ch = uartrdreg(up, Data) & 0xff; if(cq->putc) (*cq->putc)(cq, ch); else { putc(cq, ch); if(up->delim[ch/8] & (1<<(ch&7)) ) wakeup(&cq->r); } break; case 2: /* transmitter empty */ cq = up->oq; lock(cq); ch = getc(cq); if(ch < 0){ up->printing = 0;
1991/0801		wakeup(&cq->r);
1991/0810		}else outb(up->port + Data, ch); unlock(cq); break; case 0: /* modem status */ l = uartrdreg(up, Mstat); break; default: if(s&1) return; print("weird modem interrupt\n"); break;
1991/0801		}
1991/0806		l = uartrdreg(up, Lstat);
1991/0801		}
1991/0806		/* * send next output character */ if(up->printing && (l&Outready)){ cq = up->oq; lock(cq); ch = getc(cq); if(ch < 0){ up->printing = 0; wakeup(&cq->r); }else outb(up->port + Data, ch); unlock(cq); }
1991/0801		} void uartintr0(Ureg *ur) {
1991/0807		if(uart[0].enabled) uartintr(&uart[0]);
1991/0810		uartintr(&uart[0]);
1991/0801		} void uartintr1(Ureg *ur) {
1991/0808		if(uart[1].enabled) uartintr(&uart[1]);
1991/0810		uartintr(&uart[1]);
1991/0801		} /*
1991/0808/sys/src/9/pc/devuart.c:271,278 – 1991/0810/sys/src/9/pc/devuart.c:284,291
1991/0807		/*
1991/0808		* speed up the clock to poll the uart */ fclockinit();
1991/0810		*/
1991/0808		/*
1991/0801		* set up i/o routines
1991/0808/sys/src/9/pc/devuart.c:285,297 – 1991/0810/sys/src/9/pc/devuart.c:298,309
1991/0801		up->iq->ptr = up; }
1991/0807		up->enabled = 1;
1991/0808		up->sticky[Iena] = 0xf;
1991/0801		/* * turn on interrupts */
1991/0810		up->sticky[Iena] = 0x7;
1991/0801		uartwrreg(up, Iena, 0);
1991/0808		uartwrreg(up, Tctl, 0x0);
1991/0801		/* * turn on DTR and RTS
1991/0808/sys/src/9/pc/devuart.c:298,305 – 1991/0810/sys/src/9/pc/devuart.c:310,315
1991/0801		*/ uartdtr(up, 1); uartrts(up, 1);
1991/0808		print("uart enabled: Iena=%lux\n", uartrdreg(up, Iena));
1991/0807		}
1991/0806
1991/0807		/*
1991/0808/sys/src/9/pc/devuart.c:392,400 – 1991/0810/sys/src/9/pc/devuart.c:402,407
1991/0801		{ Uart *up; char name[NAMELEN];
1991/0806		print("uartstopen: q=0x%ux, inuse=%d, type=%d, dev=%d, id=%d\n",
1991/0801		q, s->inuse, s->type, s->dev, s->id);
1991/0806
1991/0801		up = &uart[s->id];
1991/0808		up->iq->putc = 0;