1992/0913/pc/devether.c (diff list | history)

1992/0909/sys/src/9/pc/devether.c:20,26 – 1992/0913/sys/src/9/pc/devether.c:20,25 (short | long | prev | next)
1992/0909		void (*receive)(Ctlr*); void (*transmit)(Ctlr*); void (*intr)(Ureg*); void (*tweek)(Ctlr*);
1992/0424		int addr; /* interface address */
1992/0501		uchar *ram; /* interface shared memory address */
1992/0906		int bt16; /* true if a 16 bit interface */
1992/0909/sys/src/9/pc/devether.c:465,472 – 1992/0913/sys/src/9/pc/devether.c:464,470
1992/0403		}
1992/0404		cp->kproc = 1;
1992/0403		for(;;){
1992/0909		tsleep(&cp->rr, isinput, cp, 1000); (*cp->hw->tweek)(cp);
1992/0913		sleep(&cp->rr, isinput, cp);
1992/0424
1992/0406		/* * process any internal loopback packets
1992/0909/sys/src/9/pc/devether.c:713,752 – 1992/0913/sys/src/9/pc/devether.c:711,716
1992/0424		}
1992/0403
1992/0505		static void
1992/0909		wd8013tweek(Ctlr *cp) { uchar laar, msr; Hw *hw = cp->hw; Buffer *tb; int s;                  s = splhi(); msr = IN(hw, msr); if(msr & MENB){ splx(s); return; } print("TWEEK\n"); delay(500);                  /* reset the hardware */ OUT(hw, msr, MENB|msr); laar = IN(hw, laar); if(hw->bt16) OUT(hw, laar, laar|L16EN); (*hw->init)(cp); (*cp->hw->online)(cp, 1);                  /* retransmit the current packet */ tb = &cp->tb[cp->ti]; if(tb->owner == Interface){ tb->busy = 0; (*cp->hw->transmit)(cp); } splx(s); }                  static void
1992/0505		dp8390rinit(Ctlr *cp) { Hw *hw = cp->hw;
1992/0909/sys/src/9/pc/devether.c:962,967 – 1992/0913/sys/src/9/pc/devether.c:926,930
1992/0424		wd8013receive, wd8013transmit, wd8013intr,
1992/0909		wd8013tweek, 0x360, /* I/O base address */
1992/0424		};