1992/1210/pc/devuart.c (diff list | history)

1992/1017/sys/src/9/pc/devuart.c:45,50 – 1992/1210/sys/src/9/pc/devuart.c:45,58 (short | long | prev | next)
1991/0823		Ferror=(1<<3), /* rcv framing error */
1991/0803		Outready=(1<<5), /* output buffer full */
1991/0801		Mstat= 6, /* modem status */
1992/1210		Ctsc= (1<<0), /* clear to send changed */ Dsrc= (1<<1), /* data set ready changed */ Rire= (1<<2), /* rising edge of ring indicator */ Dcdc= (1<<3), /* data carrier detect changed */ Cts= (1<<4), /* complement of clear to send line */ Dsr= (1<<5), /* complement of data set ready line */ Ring= (1<<6), /* complement of ring indicator line */ Dcd= (1<<7), /* complement of data carrier detect line */
1991/0801		Scratch=7, /* scratchpad */ Dlsb= 0, /* divisor lsb */ Dmsb= 1, /* divisor msb */
1992/1017/sys/src/9/pc/devuart.c:61,66 – 1992/1210/sys/src/9/pc/devuart.c:69,75
1991/0804		uchar sticky[8]; /* sticky write register values */
1991/0801		int printing; /* true if printing */
1991/0807		int enabled;
1992/1210		int cts;
1991/0801		/* console interface */
1992/1017		int special; /* can't use the stream interface */
1992/1017/sys/src/9/pc/devuart.c:199,204 – 1992/1210/sys/src/9/pc/devuart.c:208,231
1992/1016		} /*
1992/1210		* modem flow control on/off (rts/cts) */ void uartmflow(Uart *up, int n) { if(n){ up->sticky[Iena] |= Imstat; uartwrreg(up, Iena, 0); up->cts = uartrdreg(up, Mstat) & Cts; } else { up->sticky[Iena] &= ~Imstat; uartwrreg(up, Iena, 0); up->cts = 1; } } /*
1991/0801		* default is 9600 baud, 1 stop bit, 8 bit chars, no interrupts, * transmit and receive enabled, interrupts disabled. */
1992/1017/sys/src/9/pc/devuart.c:245,255 – 1992/1210/sys/src/9/pc/devuart.c:272,284
1991/0801		uartputs(IOQ *cq, char *s, int n) { Uart *up = cq->ptr;
1992/0711		int ch, x;
1992/1210		int ch, x, multiprocessor;
1991/0803		int tries;
1991/0801
1992/1210		multiprocessor = active.machs > 1;
1991/0801		x = splhi(); lock(cq);
1992/1210		if(multiprocessor) lock(cq);
1991/0801		puts(cq, s, n); if(up->printing == 0){ ch = getc(cq);
1992/1017/sys/src/9/pc/devuart.c:261,267 – 1992/1210/sys/src/9/pc/devuart.c:290,297
1991/0801		outb(up->port + Data, ch); } } unlock(cq);
1992/1210		if(multiprocessor) unlock(cq);
1991/0801		splx(x); }
1992/1017/sys/src/9/pc/devuart.c:273,280 – 1992/1210/sys/src/9/pc/devuart.c:303,311
1991/0801		{ int ch; IOQ *cq;
1991/0806		int s, l;
1992/1210		int s, l, multiprocessor;
1991/0801
1992/1210		multiprocessor = active.machs > 1;
1991/0810		for(;;){ s = uartrdreg(up, Istat); switch(s){
1992/1017/sys/src/9/pc/devuart.c:301,318 – 1992/1210/sys/src/9/pc/devuart.c:332,373
1991/0810		cq = up->oq;
1992/0409		if(cq == 0) break;
1991/0810		lock(cq); ch = getc(cq); if(ch < 0){
1992/1210		if(multiprocessor) lock(cq); if(up->cts == 0)
1991/0810		up->printing = 0;
1991/0801		wakeup(&cq->r);
1991/0810		}else outb(up->port + Data, ch); unlock(cq);
1992/1210		else { ch = getc(cq); if(ch < 0){ up->printing = 0; wakeup(&cq->r); }else outb(up->port + Data, ch); } if(multiprocessor) unlock(cq);
1991/0810		break; case 0: /* modem status */
1991/0904		uartrdreg(up, Mstat);
1992/1210		ch = uartrdreg(up, Mstat); if(ch & Ctsc){ up->cts = ch & Cts; cq = up->oq; if(cq == 0) break; if(multiprocessor) lock(cq); if(up->cts && up->printing == 0){ ch = getc(cq); if(ch >= 0){ up->printing = 1; outb(up->port + Data, getc(cq)); } else wakeup(&cq->r); } if(multiprocessor) unlock(cq); }
1991/0810		break; default:
1992/1017/sys/src/9/pc/devuart.c:390,395 – 1992/1210/sys/src/9/pc/devuart.c:445,455
1991/0801		*/ uartdtr(up, 1); uartrts(up, 1);
1992/1210		/* * assume we can send */ up->cts = 1;
1991/0807		}
1991/0806
1991/0807		/*
1992/1017/sys/src/9/pc/devuart.c:547,552 – 1992/1210/sys/src/9/pc/devuart.c:607,616
1992/1016		case 'L': case 'l': uartbits(up, n);
1992/1210		break; case 'm': case 'M': uartmflow(up, n);
1992/1016		break; case 'P': case 'p':