1993/0905/carrera/main.c (diff list | history)

1993/0904/sys/src/9/carrera/main.c:40,54 – 1993/0905/sys/src/9/carrera/main.c:40,50 (short | long | prev | next)
1993/0903		confinit(); savefpregs(&initfp); machinit(); active.exiting = 0; active.machs = 1; kmapinit(); xinit();
1993/0905		iomapinit();
1993/0903		printinit();
1993/0904		NS16552setup(Uart1, UartFREQ);
1993/0903		NS16552special(0, 9600, &kbdq, &printq, kbdcr2nl);
1993/0904
1993/0905		serialinit();
1993/0903		vecinit(); iprint("\n\nBrazil\n"); pageinit();
1993/0904/sys/src/9/carrera/main.c:58,63 – 1993/0905/sys/src/9/carrera/main.c:54,63
1993/0903		rootfiles(); swapinit(); userinit();
1993/0905		enab(); spllo(); for(;;) ;
1993/0903		schedinit(); }
1993/0904/sys/src/9/carrera/main.c:143,152 – 1993/0905/sys/src/9/carrera/main.c:143,166
1993/0903		n = m->machno; m->stb = &stlb[n][0];
1993/0904
1993/0905		m->speed = 50;
1993/0903		clockinit();
1993/0905		active.exiting = 0; active.machs = 1;
1993/0903		} /*
1993/0905		* Set up a console on serial port 2 */ void serialinit(void) { NS16552setup(Uart1, UartFREQ); NS16552special(0, 9600, &kbdq, &printq, kbdcr2nl); } /*
1993/0903		* Map IO address space in wired down TLB entry 1 */ void
1993/0904/sys/src/9/carrera/main.c:166,175 – 1993/0905/sys/src/9/carrera/main.c:180,222
1993/0904		phys = PPN(Intctlphys)|PTEGLOBL|PTEVALID|PTEWRITE|PTEUNCACHED; puttlbx(2, Intctlvirt, phys, PTEGLOBL, PGSZ4K); *(ushort*)Intenareg = 0xffff;
1993/0905		/* Enable all devce interrupt */ IO(ushort, Intenareg) = 0xffff;
1993/0903		}
1993/0905		void enetaddr(uchar *ea) { /** BUG get from PROM */ static uchar tea[] = { 0x00, 0x00, 0x77, 0x01, 0xD2, 0xba }; memmove(ea, tea, sizeof(tea)); }
1993/0903		/*
1993/0905		* All DMA and ether IO buffers must reside in the first 16M bytes of * memory to be covered by the translation registers */ void iomapinit(void) { int i; Tte *t; t = xspanalloc(Ntranslation*sizeof(Tte), BY2PG, 0); for(i = 0; i < Ntranslation; i++) t[i].lo = i<<PGSHIFT; /* Set the translation table */ IO(ulong, Ttbr) = PADDR(t); IO(ulong, Tlrb) = (Ntranslation-1)*sizeof(Tte); /* Invalidate the old entries */ IO(ulong, Tir) = 0; } /*
1993/0903		* setup MIPS trap vectors */ void
1993/0904/sys/src/9/carrera/main.c:272,281 – 1993/0905/sys/src/9/carrera/main.c:319,328
1993/0903		void exit(long type) { int timer;
1993/0905		USED(type);
1993/0903		spllo(); print("cpu %d exiting %d\n", m->machno, type);
1993/0905		print("cpu %d exiting\n", m->machno);
1993/0904		while(consactive())
1993/0903		delay(10); splhi();
1993/0904/sys/src/9/carrera/main.c:288,298 – 1993/0905/sys/src/9/carrera/main.c:335,340
1993/0903		{ ulong ktop, top; /* * divide memory twixt user pages and kernel. Since * the kernel can't use anything above .5G unmapped, * make sure all that memory goes to the user. */ ktop = PGROUND((ulong)end); ktop = PADDR(ktop); top = (16*1024*1024)/BY2PG;
1993/0904/sys/src/9/carrera/main.c:306,313 – 1993/0905/sys/src/9/carrera/main.c:348,353
1993/0903		conf.base1 = 0;
1993/0904		conf.upages = (conf.npage*70)/100;
1993/0903		if(top - conf.upages > (256*1024*1024)/BY2PG) conf.upages = top - (256*1024*1024)/BY2PG; conf.nmach = 1;
1993/0904/sys/src/9/carrera/main.c:320,326 – 1993/0905/sys/src/9/carrera/main.c:360,366
1993/0903		conf.arp = 32; conf.frag = 32; conf.copymode = 0; /* copy on reference */
1993/0905		conf.copymode = 0; /* copy on write */
1993/0903		}