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1993/0915/pc/ether8390.c (diff list | history)

pc/ether8390.c on 1992/1222
1992/1222    
/* 
 * National Semiconductor DP8390 
 * and SMC 83C90 
 * Network Interface Controller. 
 */ 
#include "u.h" 
#include "../port/lib.h" 
#include "mem.h" 
#include "dat.h" 
#include "fns.h" 
#include "../port/error.h" 
#include "io.h" 
#include "devtab.h" 
 
#include "ether.h" 
 
enum { 
	Cr		= 0x00,		/* command register, all pages */ 
 
	Stp		= 0x01,		/* stop */ 
	Sta		= 0x02,		/* start */ 
	Txp		= 0x04,		/* transmit packet */ 
	RDMAread	= (1<<3),	/* remote DMA read */ 
	RDMAwrite	= (2<<3),	/* remote DMA write */ 
	RDMAsend	= (3<<3),	/* remote DMA send packet */ 
	RDMAabort	= (4<<3),	/* abort/complete remote DMA */
1993/0212    
	Ps0		= 0x40,		/* page select */ 
	Ps1		= 0x80,		/* page select */ 
	Page0		= 0x00, 
	Page1		= Ps0, 
	Page2		= Ps1,
1992/1222    
}; 
 
enum {					/* Page 0, read */ 
	Clda0		= 0x01,		/* current local DMA address 0 */ 
	Clda1		= 0x02,		/* current local DMA address 1 */ 
	Bnry		= 0x03,		/* boundary pointer (R/W) */ 
	Tsr		= 0x04,		/* transmit status register */ 
	Ncr		= 0x05,		/* number of collisions register */ 
	Fifo		= 0x06,		/* FIFO */ 
	Isr		= 0x07,		/* interrupt status register (R/W) */ 
	Crda0		= 0x08,		/* current remote DMA address 0 */
1993/0212    
	Crda1		= 0x09,		/* current remote DMA address 1 */
1992/1222    
	Rsr		= 0x0C,		/* receive status register */ 
	Cntr0		= 0x0D,		/* frame alignment errors */ 
	Cntr1		= 0x0E,		/* CRC errors */ 
	Cntr2		= 0x0F,		/* missed packet errors */ 
}; 
 
enum {					/* Page 0, write */ 
	Pstart		= 0x01,		/* page start register */ 
	Pstop		= 0x02,		/* page stop register */ 
	Tpsr		= 0x04,		/* transmit page start address */ 
	Tbcr0		= 0x05,		/* transmit byte count register 0 */ 
	Tbcr1		= 0x06,		/* transmit byte count register 1 */ 
	Rsar0		= 0x08,		/* remote start address register 0 */ 
	Rsar1		= 0x09,		/* remote start address register 1 */ 
	Rbcr0		= 0x0A,		/* remote byte count register 0 */ 
	Rbcr1		= 0x0B,		/* remote byte count register 1 */ 
	Rcr		= 0x0C,		/* receive configuration register */ 
	Tcr		= 0x0D,		/* transmit configuration register */ 
	Dcr		= 0x0E,		/* data configuration register */ 
	Imr		= 0x0F,		/* interrupt mask */ 
}; 
 
enum {					/* Page 1, read/write */ 
	Par0		= 0x01,		/* physical address register 0 */ 
	Curr		= 0x07,		/* current page register */ 
	Mar0		= 0x08,		/* multicast address register 0 */ 
}; 
 
enum {					/* Interrupt Status Register */ 
	Prx		= 0x01,		/* packet received */ 
	Ptx		= 0x02,		/* packet transmitted */ 
	Rxe		= 0x04,		/* receive error */ 
	Txe		= 0x08,		/* transmit error */ 
	Ovw		= 0x10,		/* overwrite warning */ 
	Cnt		= 0x20,		/* counter overflow */ 
	Rdc		= 0x40,		/* remote DMA complete */ 
	Rst		= 0x80,		/* reset status */ 
}; 
 
enum {					/* Interrupt Mask Register */ 
	Prxe		= 0x01,		/* packet received interrupt enable */ 
	Ptxe		= 0x02,		/* packet transmitted interrupt enable */ 
	Rxee		= 0x04,		/* receive error interrupt enable */ 
	Txee		= 0x08,		/* transmit error interrupt enable */ 
	Ovwe		= 0x10,		/* overwrite warning interrupt enable */ 
	Cnte		= 0x20,		/* counter overflow interrupt enable */ 
	Rdce		= 0x40,		/* DMA complete interrupt enable */ 
}; 
 
enum {					/* Data Configuration register */ 
	Wts		= 0x01,		/* word transfer select */ 
	Bos		= 0x02,		/* byte order select */ 
	Las		= 0x04,		/* long address select */ 
	Ls		= 0x08,		/* loopback select */ 
	Arm		= 0x10,		/* auto-initialise remote */ 
	Ft1		= (0x00<<5),	/* FIFO threshhold select 1 byte/word */ 
	Ft2		= (0x01<<5),	/* FIFO threshhold select 2 bytes/words */ 
	Ft4		= (0x02<<5),	/* FIFO threshhold select 4 bytes/words */ 
	Ft6		= (0x03<<5),	/* FIFO threshhold select 6 bytes/words */ 
}; 
 
enum {					/* Transmit Configuration Register */ 
	Crc		= 0x01,		/* inhibit CRC */ 
	Lb		= 0x02,		/* internal loopback */ 
	Atd		= 0x08,		/* auto transmit disable */ 
	Ofst		= 0x10,		/* collision offset enable */ 
}; 
 
enum {					/* Transmit Status Register */ 
	Ptxok		= 0x01,		/* packet transmitted */ 
	Col		= 0x04,		/* transmit collided */ 
	Abt		= 0x08,		/* tranmit aborted */ 
	Crs		= 0x10,		/* carrier sense lost */ 
	Fu		= 0x20,		/* FIFO underrun */ 
	Cdh		= 0x40,		/* CD heartbeat */ 
	Owc		= 0x80,		/* out of window collision */ 
}; 
 
enum {					/* Receive Configuration Register */ 
	Sep		= 0x01,		/* save errored packets */ 
	Ar		= 0x02,		/* accept runt packets */ 
	Ab		= 0x04,		/* accept broadcast */ 
	Am		= 0x08,		/* accept multicast */ 
	Pro		= 0x10,		/* promiscuous physical */ 
	Mon		= 0x20,		/* monitor mode */ 
}; 
 
enum {					/* Receive Status Register */ 
	Prxok		= 0x01,		/* packet received intact */ 
	Crce		= 0x02,		/* CRC error */ 
	Fae		= 0x04,		/* frame alignment error */ 
	Fo		= 0x08,		/* FIFO overrun */ 
	Mpa		= 0x10,		/* missed packet */ 
	Phy		= 0x20,		/* physical/multicast address */ 
	Dis		= 0x40,		/* receiver disabled */ 
	Dfr		= 0x80,		/* deferring */ 
}; 
 
typedef struct { 
	uchar	status; 
	uchar	next; 
	uchar	len0; 
	uchar	len1; 
} Hdr; 
 
static void 
dp8390disable(Ctlr *ctlr) 
{
1993/0915    
	ulong dp8390;
1992/1222    
	int timo;
1993/0915    
	dp8390 = ctlr->card.dp8390;
1992/1222    
	/* 
	 * Stop the chip. Set the Stp bit and wait for the chip 
	 * to finish whatever was on its tiny mind before it sets 
	 * the Rst bit. 
	 * We need the timeout because there may not be a real 
	 * chip there if this is called when probing for a device 
	 * at boot. 
	 */
1993/0915    
	dp8390outb(dp8390+Cr, Page0|RDMAabort|Stp); 
	dp8390outb(dp8390+Rbcr0, 0); 
	dp8390outb(dp8390+Rbcr1, 0); 
	for(timo = 10000; (dp8390inb(dp8390+Isr) & Rst) == 0 && timo; timo--)
1992/1222    
			; 
}
1993/0212    
static void 
dp8390ring(Ctlr *ctlr) 
{
1993/0915    
	ulong dp8390;
1993/0212    
1993/0915    
	dp8390 = ctlr->card.dp8390; 
	dp8390outb(dp8390+Pstart, ctlr->card.pstart); 
	dp8390outb(dp8390+Pstop, ctlr->card.pstop); 
	dp8390outb(dp8390+Bnry, ctlr->card.pstop-1);
1993/0212    
1993/0915    
	dp8390outb(dp8390+Cr, Page1|RDMAabort|Stp); 
	dp8390outb(dp8390+Curr, ctlr->card.pstart); 
	dp8390outb(dp8390+Cr, Page0|RDMAabort|Stp);
1993/0212    
	ctlr->card.nxtpkt = ctlr->card.pstart; 
}
1992/1222    
void 
dp8390reset(Ctlr *ctlr) 
{
1993/0915    
	ulong dp8390; 
 
	dp8390 = ctlr->card.dp8390;
1992/1222    
	/* 
	 * This is the initialisation procedure described
1993/0212    
	 * as 'mandatory' in the datasheet, with references 
	 * to the 3Com503 technical reference manual.
1992/1222    
	 */  
	dp8390disable(ctlr);
1993/0212    
	if(ctlr->card.bit16)
1993/0915    
		dp8390outb(dp8390+Dcr, Ft4|Ls|Wts);
1992/1222    
	else
1993/0915    
		dp8390outb(dp8390+Dcr, Ft4|Ls);
1992/1222    
1993/0915    
	dp8390outb(dp8390+Rbcr0, 0); 
	dp8390outb(dp8390+Rbcr1, 0);
1992/1222    
1993/0915    
	dp8390outb(dp8390+Tcr, 0); 
	dp8390outb(dp8390+Rcr, Mon);
1992/1222    
 
	/*
1993/0212    
	 * Init the ring hardware and software ring pointers. 
	 * Can't initialise ethernet address as we may not know 
	 * it yet.
1992/1222    
	 */
1993/0212    
	dp8390ring(ctlr);
1993/0915    
	dp8390outb(dp8390+Tpsr, ctlr->card.tstart);
1992/1222    
1993/0915    
	dp8390outb(dp8390+Isr, 0xFF); 
	dp8390outb(dp8390+Imr, Cnte|Ovwe|Txee|Rxee|Ptxe|Prxe);
1993/0212    
1992/1222    
	/* 
	 * Leave the chip initialised,
1993/0213    
	 * but in monitor mode.
1992/1222    
	 */
1993/0915    
	dp8390outb(dp8390+Cr, Page0|RDMAabort|Sta);
1992/1222    
} 
 
void 
dp8390attach(Ctlr *ctlr) 
{ 
	/* 
	 * Enable the chip for transmit/receive.
1993/0212    
	 * The init routine leaves the chip in monitor
1993/0213    
	 * mode. Clear the missed-packet counter, it 
	 * increments while in monitor mode.
1992/1222    
	 */
1993/0212    
	dp8390outb(ctlr->card.dp8390+Rcr, Ab);
1993/0213    
	dp8390inb(ctlr->card.dp8390+Cntr2);
1992/1222    
} 
 
void 
dp8390mode(Ctlr *ctlr, int on) 
{
1993/0212    
	/* 
	 * Set/reset promiscuous mode. 
	 */
1992/1222    
	if(on)
1993/0212    
		dp8390outb(ctlr->card.dp8390+Rcr, Pro|Ab);
1992/1222    
	else
1993/0212    
		dp8390outb(ctlr->card.dp8390+Rcr, Ab);
1992/1222    
} 
 
void 
dp8390setea(Ctlr *ctlr) 
{
1993/0915    
	ulong dp8390;
1992/1222    
	uchar cr; 
	int i;
1993/0915    
	dp8390 = ctlr->card.dp8390;
1992/1222    
	/* 
	 * Set the ethernet address into the chip. 
	 * Take care to restore the command register 
	 * afterwards. We don't care about multicast 
	 * addresses as we never set the multicast 
	 * enable. 
	 */
1993/0915    
	cr = dp8390inb(dp8390+Cr) & ~Txp; 
	dp8390outb(dp8390+Cr, Page1|(~(Ps1|Ps0) & cr));
1992/1222    
	for(i = 0; i < sizeof(ctlr->ea); i++)
1993/0915    
		dp8390outb(dp8390+Par0+i, ctlr->ea[i]); 
	dp8390outb(dp8390+Cr, cr);
1992/1222    
}
1993/0915    
void 
dp8390getea(Ctlr *ctlr) 
{ 
	ulong dp8390; 
	uchar cr; 
	int i; 
 
	dp8390 = ctlr->card.dp8390; 
	/* 
	 * Set the ethernet address into the chip. 
	 * Take care to restore the command register 
	 * afterwards. We don't care about multicast 
	 * addresses as we never set the multicast 
	 * enable. 
	 */ 
	cr = dp8390inb(dp8390+Cr) & ~Txp; 
	dp8390outb(dp8390+Cr, Page1|(~(Ps1|Ps0) & cr)); 
	for(i = 0; i < sizeof(ctlr->ea); i++) 
		ctlr->ea[i] = dp8390inb(dp8390+Par0+i); 
	dp8390outb(dp8390+Cr, cr); 
}
1992/1222    
void* 
dp8390read(Ctlr *ctlr, void *to, ulong from, ulong len) 
{
1993/0915    
	ulong dp8390;
1992/1222    
	uchar cr; 
	int timo;
1993/0915    
	dp8390 = ctlr->card.dp8390;
1992/1222    
	/*
1993/0212    
	 * Read some data at offset 'from' in the card's memory
1992/1222    
	 * using the DP8390 remote DMA facility, and place it at 
	 * 'to' in main memory, via the I/O data port. 
	 */
1993/0915    
	cr = dp8390inb(dp8390+Cr) & ~Txp; 
	dp8390outb(dp8390+Cr, Page0|RDMAabort|Sta); 
	dp8390outb(dp8390+Isr, Rdc);
1992/1222    
 
	/* 
	 * Set up the remote DMA address and count. 
	 */
1993/0212    
	if(ctlr->card.bit16)
1992/1222    
		len = ROUNDUP(len, 2);
1993/0915    
	dp8390outb(dp8390+Rbcr0, len & 0xFF); 
	dp8390outb(dp8390+Rbcr1, (len>>8) & 0xFF); 
	dp8390outb(dp8390+Rsar0, from & 0xFF); 
	dp8390outb(dp8390+Rsar1, (from>>8) & 0xFF);
1992/1222    
 
	/* 
	 * Start the remote DMA read and suck the data 
	 * out of the I/O port. 
	 */
1993/0915    
	dp8390outb(dp8390+Cr, Page0|RDMAread|Sta);
1993/0212    
	if(ctlr->card.bit16) 
		inss(ctlr->card.data, to, len/2);
1992/1222    
	else
1993/0212    
		insb(ctlr->card.data, to, len);
1992/1222    
 
	/* 
	 * Wait for the remote DMA to complete. The timeout 
	 * is necessary because we may call this routine on 
	 * a non-existent chip during initialisation and, due 
	 * to the miracles of the bus, we could get this far 
	 * and still be talking to a slot full of nothing. 
	 */
1993/0915    
	for(timo = 10000; (dp8390inb(dp8390+Isr) & Rdc) == 0 && timo; timo--)
1992/1222    
			;
1993/0915    
	dp8390outb(dp8390+Isr, Rdc); 
	dp8390outb(dp8390+Cr, cr);
1992/1222    
	return to; 
} 
 
void* 
dp8390write(Ctlr *ctlr, ulong to, void *from, ulong len) 
{
1993/0915    
	ulong dp8390, crda;
1992/1222    
	uchar cr;
1993/0915    
	dp8390 = ctlr->card.dp8390;
1992/1222    
	/*
1993/0212    
	 * Write some data to offset 'to' in the card's memory
1992/1222    
	 * using the DP8390 remote DMA facility, reading it at 
	 * 'from' in main memory, via the I/O data port. 
	 */
1993/0915    
	cr = dp8390inb(dp8390+Cr) & ~Txp; 
	dp8390outb(dp8390+Cr, Page0|RDMAabort|Sta); 
	dp8390outb(dp8390+Isr, Rdc);
1992/1222    
1993/0212    
	if(ctlr->card.bit16) 
		len = ROUNDUP(len, 2);
1992/1222    
	/* 
	 * Set up the remote DMA address and count.
1993/0212    
	 * This is straight from the DP8390[12D] datasheet, hence 
	 * the initial set up for read.
1992/1222    
	 */
1993/0212    
	crda = to-1-ctlr->card.bit16;
1993/0915    
	dp8390outb(dp8390+Rbcr0, (len+1+ctlr->card.bit16) & 0xFF); 
	dp8390outb(dp8390+Rbcr1, ((len+1+ctlr->card.bit16)>>8) & 0xFF); 
	dp8390outb(dp8390+Rsar0, crda & 0xFF); 
	dp8390outb(dp8390+Rsar1, (crda>>8) & 0xFF); 
	dp8390outb(dp8390+Cr, Page0|RDMAread|Sta);
1992/1222    
1993/0212    
	for(;;){
1993/0915    
		crda = dp8390inb(dp8390+Crda0); 
		crda |= dp8390inb(dp8390+Crda1)<<8;
1993/0212    
		if(crda == to){ 
			/* 
			 * Start the remote DMA write and make sure 
			 * the registers are correct. 
			 */
1993/0915    
			dp8390outb(dp8390+Cr, Page0|RDMAwrite|Sta);
1992/1222    
1993/0915    
			crda = dp8390inb(dp8390+Crda0); 
			crda |= dp8390inb(dp8390+Crda1)<<8;
1993/0212    
			if(crda != to) 
				panic("crda write %d to %d\n", crda, to); 
 
			break; 
		} 
	}
1992/1222    
	/*
1993/0212    
	 * Pump the data into the I/O port.
1992/1222    
	 */
1993/0212    
	if(ctlr->card.bit16) 
		outss(ctlr->card.data, from, len/2);
1992/1222    
	else
1993/0212    
		outsb(ctlr->card.data, from, len);
1992/1222    
 
	/* 
	 * Wait for the remote DMA to finish. We'll need 
	 * a timeout here if this ever gets called before 
	 * we know there really is a chip there. 
	 */
1993/0915    
	while((dp8390inb(dp8390+Isr) & Rdc) == 0)
1992/1222    
			;
1993/0915    
	dp8390outb(dp8390+Isr, Rdc); 
	dp8390outb(dp8390+Cr, cr);
1992/1222    
	return (void*)to; 
}
1993/0212    
static uchar
1993/0915    
getcurr(ulong dp8390)
1993/0212    
{ 
	uchar cr, curr;
1993/0915    
	cr = dp8390inb(dp8390+Cr) & ~Txp; 
	dp8390outb(dp8390+Cr, Page1|(~(Ps1|Ps0) & cr)); 
	curr = dp8390inb(dp8390+Curr); 
	dp8390outb(dp8390+Cr, cr);
1993/0212    
	return curr; 
}
1993/0213    
static void
1993/0915    
cldaquiet(ulong dp8390)
1993/0213    
{ 
	uchar a, b, c; 
 
	/* 
	 * Hack to keep away from the card's memory while it is receiving 
	 * a packet. This is only a problem on the NCR 3170 Safari. 
	 * 
	 * We peek at the current local DMA registers and, if they are 
	 * changing, wait. 
	 */ 
	 
	for(;;delay(10)){
1993/0915    
		a = dp8390inb(dp8390+Clda0); 
		b = dp8390inb(dp8390+Clda0);
1993/0213    
		if(a != b) 
			continue;
1993/0915    
		c = dp8390inb(dp8390+Clda0);
1993/0213    
		if(c != b) 
			continue; 
		break; 
	} 
}
1992/1222    
void 
dp8390receive(Ctlr *ctlr) 
{ 
	RingBuf *ring;
1993/0212    
	uchar curr, len1, *pkt;
1992/1222    
	Hdr hdr;
1993/0915    
	ulong dp8390, data, len;
1992/1222    
1993/0915    
	dp8390 = ctlr->card.dp8390; 
	for(curr = getcurr(dp8390); ctlr->card.nxtpkt != curr; curr = getcurr(dp8390)){
1993/0213    
		if(strcmp(arch->id, "NCRD.0") == 0)
1993/0915    
			cldaquiet(dp8390);
1992/1222    
 
		ctlr->inpackets++;
1993/0212    
		data = ctlr->card.nxtpkt*Dp8390BufSz; 
		(*ctlr->card.read)(ctlr, &hdr, data, sizeof(Hdr));
1992/1222    
 
		/*
1993/0212    
		 * Don't believe the upper byte count, work it 
		 * out from the software next-page pointer and 
		 * the current next-page pointer.
1992/1222    
		 */
1993/0212    
		if(hdr.next > ctlr->card.nxtpkt) 
			len1 = hdr.next - ctlr->card.nxtpkt - 1; 
		else 
			len1 = (ctlr->card.pstop-ctlr->card.nxtpkt) + (hdr.next-ctlr->card.pstart) - 1; 
		if(hdr.len0 > (Dp8390BufSz-sizeof(Hdr))) 
			len1--; 
 
		len = ((len1<<8)|hdr.len0)-4; 
 
		/* 
		 * Chip is badly scrogged, reinitialise the ring. 
		 */ 
		if(hdr.next < ctlr->card.pstart || hdr.next >= ctlr->card.pstop 
		  || len < 60 || len > sizeof(Etherpkt)){ 
			print("H#%2.2ux#%2.2ux#%2.2ux#%2.2ux,%d|", 
				hdr.status, hdr.next, hdr.len0, hdr.len1, len);
1993/0915    
			dp8390outb(dp8390+Cr, Page0|RDMAabort|Stp);
1993/0212    
			dp8390ring(ctlr);
1993/0915    
			dp8390outb(dp8390+Cr, Page0|RDMAabort|Sta);
1992/1222    
			return; 
		}
1993/0212    
		/* 
		 * If it's a good packet and we have a place to put it, 
		 * read it in to the software ring. 
		 * If the packet wraps round the hardware ring, read it 
		 * in two pieces. 
		 */
1992/1222    
		ring = &ctlr->rb[ctlr->ri];
1993/0212    
		if((hdr.status & (Fo|Fae|Crce|Prxok)) == Prxok && ring->owner == Interface){ 
			pkt = ring->pkt;
1992/1222    
			data += sizeof(Hdr);
1993/0212    
			ring->len = len; 
 
			if((data+len) >= ctlr->card.pstop*Dp8390BufSz){ 
				ulong count = ctlr->card.pstop*Dp8390BufSz - data; 
 
				(*ctlr->card.read)(ctlr, pkt, data, count); 
				pkt += count; 
				data = ctlr->card.pstart*Dp8390BufSz; 
				len -= count;
1992/1222    
			}
1993/0212    
			if(len) 
				(*ctlr->card.read)(ctlr, pkt, data, len);
1992/1222    
			ring->owner = Host; 
			ctlr->ri = NEXT(ctlr->ri, ctlr->nrb); 
		}
1993/0212    
		/* 
		 * Finished woth this packet, update the 
		 * hardware and software ring pointers. 
		 */ 
		ctlr->card.nxtpkt = hdr.next; 
 
		hdr.next--; 
		if(hdr.next < ctlr->card.pstart) 
			hdr.next = ctlr->card.pstop-1;
1993/0915    
		dp8390outb(dp8390+Bnry, hdr.next);
1992/1222    
	} 
}
1993/0212    
/* 
 * Initiate a transmission. Must be called splhi(). 
 */
1992/1222    
void 
dp8390transmit(Ctlr *ctlr) 
{
1993/0915    
	ulong dp8390;
1992/1222    
	RingBuf *ring;
1993/0212    
1993/0915    
	dp8390 = ctlr->card.dp8390;
1993/0212    
	ring = &ctlr->tb[ctlr->ti]; 
	if(ctlr->tbusy == 0 && ring->owner == Interface){
1993/0213    
 
		ctlr->tbusy = 1;
1993/0212    
		(*ctlr->card.write)(ctlr, ctlr->card.tstart*Dp8390BufSz, ring->pkt, ring->len);
1993/0213    
1993/0915    
		dp8390outb(dp8390+Tbcr0, ring->len & 0xFF); 
		dp8390outb(dp8390+Tbcr1, (ring->len>>8) & 0xFF); 
		dp8390outb(dp8390+Cr, Page0|RDMAabort|Txp|Sta);
1993/0212    
	} 
} 
 
void 
dp8390overflow(Ctlr *ctlr) 
{
1993/0915    
	ulong dp8390;
1993/0212    
	uchar txp; 
	int resend;
1993/0915    
	dp8390 = ctlr->card.dp8390;
1993/0212    
	/* 
	 * The following procedure is taken from the DP8390[12D] datasheet, 
	 * it seems pretty adamant that this is what has to be done. 
	 */
1993/0915    
	txp = dp8390inb(dp8390+Cr) & Txp; 
	dp8390outb(dp8390+Cr, Page0|RDMAabort|Stp);
1993/0212    
	delay(2);
1993/0915    
	dp8390outb(dp8390+Rbcr0, 0); 
	dp8390outb(dp8390+Rbcr1, 0);
1993/0212    
 
	resend = 0;
1993/0915    
	if(txp && (dp8390inb(dp8390+Isr) & (Txe|Ptx)) == 0)
1993/0212    
		resend = 1;
1993/0915    
	dp8390outb(dp8390+Tcr, Lb); 
	dp8390outb(dp8390+Cr, Page0|RDMAabort|Sta);
1993/0212    
	(*ctlr->card.receive)(ctlr);
1993/0915    
	dp8390outb(dp8390+Isr, Ovw);
1993/0212    
	wakeup(&ctlr->rr);
1993/0915    
	dp8390outb(dp8390+Tcr, 0);
1993/0212    
 
	if(resend)
1993/0915    
		dp8390outb(dp8390+Cr, Page0|RDMAabort|Txp|Sta);
1993/0212    
} 
 
void 
dp8390watch(Ctlr *ctlr) 
{
1992/1222    
	int s;
1993/0212    
	/* 
	 * Stub watchdog routine. 
	 * Whine if a transmit takes too long. 
	 */
1992/1222    
	s = splhi();
1993/0212    
	if(ctlr->tbusy){ 
		ctlr->tbusy++; 
		if(ctlr->tbusy > 1 && ctlr->debug) 
			print("TB%d|", ctlr->tbusy);
1992/1222    
	} 
	splx(s); 
} 
 
void 
dp8390intr(Ctlr *ctlr) 
{
1993/0915    
	ulong dp8390;
1992/1222    
	RingBuf *ring;
1993/0212    
	uchar isr, r;
1992/1222    
1993/0915    
	dp8390 = ctlr->card.dp8390;
1992/1222    
	/* 
	 * While there is something of interest, 
	 * clear all the interrupts and process. 
	 */
1993/0915    
	dp8390outb(dp8390+Imr, 0x00); 
	while(isr = dp8390inb(dp8390+Isr)){
1992/1222    
 
		if(isr & Ovw){
1993/0212    
			if(ctlr->card.overflow) 
				(*ctlr->card.overflow)(ctlr);
1993/0915    
			dp8390outb(dp8390+Isr, Ovw);
1992/1222    
			ctlr->overflows++; 
		} 
 
		/* 
		 * We have received packets. 
		 * Take a spin round the ring and 
		 * wakeup the kproc. 
		 */ 
		if(isr & (Rxe|Prx)){
1993/0212    
			(*ctlr->card.receive)(ctlr);
1993/0915    
			dp8390outb(dp8390+Isr, Rxe|Prx);
1992/1222    
			wakeup(&ctlr->rr); 
		} 
 
		/* 
		 * A packet completed transmission, successfully or 
		 * not. Start transmission on the next buffered packet, 
		 * and wake the output routine. 
		 */ 
		if(isr & (Txe|Ptx)){
1993/0915    
			r = dp8390inb(dp8390+Tsr);
1993/0212    
			if(isr & Txe){ 
				if((r & (Cdh|Fu|Crs|Abt)) && ctlr->debug) 
					print("Tsr#%2.2ux|", r); 
				ctlr->oerrs++; 
			}
1993/0915    
			dp8390outb(dp8390+Isr, Txe|Ptx);
1993/0212    
 
			if(isr & Ptx) 
				ctlr->outpackets++;
1992/1222    
			ring = &ctlr->tb[ctlr->ti]; 
			ring->owner = Host;
1993/0212    
			ctlr->tbusy = 0;
1992/1222    
			ctlr->ti = NEXT(ctlr->ti, ctlr->ntb);
1993/0212    
			(*ctlr->card.transmit)(ctlr);
1992/1222    
			wakeup(&ctlr->tr); 
		}
1993/0212    
 
		if(isr & Cnt){
1993/0915    
			ctlr->frames += dp8390inb(dp8390+Cntr0); 
			ctlr->crcs += dp8390inb(dp8390+Cntr1); 
			ctlr->buffs += dp8390inb(dp8390+Cntr2); 
			dp8390outb(dp8390+Isr, Cnt);
1993/0212    
		}
1992/1222    
	}
1993/0915    
	dp8390outb(dp8390+Imr, Cnte|Ovwe|Txee|Rxee|Ptxe|Prxe);
1992/1222    
}


source code copyright © 1990-2005 Lucent Technologies; see license
Plan 9 distribution
comments to russ cox (rsc@swtch.com)