1997/0327/pc/io.h (diff list | history)

1995/0818/sys/src/9/pc/io.h:1,74 – 1997/0327/sys/src/9/pc/io.h:1,153 (short | long | prev | next)
Initial SMP support — new vector names, replace PCIcfg with Pcidev, add PCMmap. rsc Fri Mar 4 12:44:25 2005
1991/0703		/*
1991/0731		* programmable interrupt vectors (for the 8259's)
1991/0703		*/
1991/0704		enum {
1991/1112		Bptvec= 3, /* breakpoints */
1991/0906		Mathemuvec= 7, /* math coprocessor emulation interrupt */ Mathovervec= 9, /* math coprocessor overrun interrupt */
1991/0912		Matherr1vec= 16, /* math coprocessor error interrupt */
1991/0710		Faultvec= 14, /* page fault */
1997/0327		#define X86STEPPING(x) ((x) & 0x0F) #define X86MODEL(x) (((x)>>4) & 0x0F) #define X86FAMILY(x) (((x)>>8) & 0x0F)
1991/0905
1991/0904		Int0vec= 24, /* first 8259 */
1991/0731		Clockvec= Int0vec+0, /* clock interrupts */ Kbdvec= Int0vec+1, /* keyboard interrupts */
1991/0810		Uart1vec= Int0vec+3, /* modem line */
1991/0811		Uart0vec= Int0vec+4, /* serial line */
1992/0929		PCMCIAvec= Int0vec+5, /* PCMCIA card change */
1991/0731		Floppyvec= Int0vec+6, /* floppy interrupts */
1991/1127		Parallelvec= Int0vec+7, /* parallel port interrupts */
1992/0904		Int1vec= Int0vec+8,
1994/0908		Vector9= Int0vec+9, /* unassigned */ Vector10= Int0vec+10, /* unassigned, usually ethernet */ Vector11= Int0vec+11, /* unassigned, usually scsi */
1992/0904		Mousevec= Int0vec+12, /* mouse interrupt */ Matherr2vec= Int0vec+13, /* math coprocessor */
1995/0818		ATAvec0= Int0vec+14, /* ATA controller #1 */ ATAvec1= Int0vec+15, /* ATA controller #2 */
1997/0327		enum { VectorBPT = 3, /* breakpoint */ VectorCNA = 7, /* coprocessor not available */ VectorCSO = 9, /* coprocessor segment overrun */ VectorPF = 14, /* page fault */ VectorCERR = 16, /* coprocessor error */
1991/0910		Syscallvec= 64,
1997/0327		VectorLAPIC = 32, /* local APIC interrupts */ VectorLINT0 = VectorLAPIC+0,/* LINT[01] must be offsets 0 and 1 */ VectorLINT1 = VectorLAPIC+1, VectorTIMER = VectorLAPIC+2, VectorERROR = VectorLAPIC+3, VectorPCINT = VectorLAPIC+4, VectorSPURIOUS = VectorLAPIC+15,/* must have bits [3-0] == 0x0F */ MaxVectorLAPIC = VectorLAPIC+15, VectorSYSCALL = 64, VectorPIC = 128, /* external [A]PIC interrupts */ VectorCLOCK = VectorPIC+0, VectorKBD = VectorPIC+1, VectorUART1 = VectorPIC+3, VectorUART0 = VectorPIC+4, VectorPCMCIA = VectorPIC+5, VectorFLOPPY = VectorPIC+6, VectorLPT = VectorPIC+7, VectorIRQ7 = VectorPIC+7, VectorAUX = VectorPIC+12, /* PS/2 port */ VectorIRQ13 = VectorPIC+13, /* coprocessor on x386 */ VectorATA0 = VectorPIC+14, MaxVectorPIC = VectorPIC+15,
1994/0908		}; enum {
1997/0327		BusCBUS = 0, /* Corollary CBUS */ BusCBUSII, /* Corollary CBUS II */ BusEISA, /* Extended ISA */ BusFUTURE, /* IEEE Futurebus */ BusINTERN, /* Internal bus */ BusISA, /* Industry Standard Architecture */ BusMBI, /* Multibus I */ BusMBII, /* Multibus II */ BusMCA, /* Micro Channel Architecture */ BusMPI, /* MPI */ BusMPSA, /* MPSA */ BusNUBUS, /* Apple Macintosh NuBus */ BusPCI, /* Peripheral Component Interconnect */ BusPCMCIA, /* PC Memory Card International Association */ BusTC, /* DEC TurboChannel */ BusVL, /* VESA Local bus */ BusVME, /* VMEbus */ BusXPRESS, /* Express System Bus */ }; #define MKBUS(t,b,d,f) (((t)<<24)|(((b)&0xFF)<<16)|(((d)&0x1F)<<11)|(((f)&0x07)<<8)) #define BUSFNO(tbdf) (((tbdf)>>8)&0x07) #define BUSDNO(tbdf) (((tbdf)>>11)&0x1F) #define BUSBNO(tbdf) (((tbdf)>>16)&0xFF) #define BUSTYPE(tbdf) ((tbdf)>>24) #define BUSBDF(tbdf) ((tbdf)&0x00FFFF00) #define BUSUNKNOWN (-1) enum {
1994/0908		MaxEISA = 16,
1995/0126		EISAconfig = 0xC80,
1991/0704		};
1995/0517		/* * PCI Local Bus support. * Quick hack until we figure out how to * deal with EISA, PCI, PCMCIA, PnP, etc.
1997/0327		* PCI support code.
1995/0517		*/ enum { /* configuration mechanism #1 */ PCIaddr = 0xCF8, /* CONFIG_ADDRESS */ PCIdata = 0xCFC, /* CONFIG_DATA */
1997/0327		enum { /* type 0 and type 1 pre-defined header */ PciVID = 0x00, /* vendor ID */ PciDID = 0x02, /* device ID */ PciPCR = 0x04, /* command */ PciPSR = 0x06, /* status */ PciRID = 0x08, /* revision ID */ PciCCRp = 0x09, /* programming interface class code */ PciCCRu = 0x0A, /* sub-class code */ PciCCRb = 0x0B, /* base class code */ PciCLS = 0x0C, /* cache line size */ PciLTR = 0x0D, /* latency timer */ PciHDT = 0x0E, /* header type */ PciBST = 0x0F, /* BIST */
1995/0517		/* configuration mechanism #2 */ PCIcse = 0xCF8, /* configuration space enable */ PCIforward = 0xCFA, /* which bus */
1995/0726		MaxPCI = 32, /* 16 for mechanism #2 */
1997/0327		PciBAR0 = 0x10, /* base address */ PciBAR1 = 0x14, PciINTL = 0x3C, /* interrupt line */ PciINTP = 0x3D, /* interrupt pin */
1995/0517		}; typedef struct PCIcfg {
1997/0327		enum { /* type 0 pre-defined header */ PciBAR2 = 0x18, PciBAR3 = 0x1C, PciBAR4 = 0x20, PciBAR5 = 0x24, PciCIS = 0x28, /* cardbus CIS pointer */ PciSVID = 0x2C, /* subsystem vendor ID */ PciSID = 0x2E, /* cardbus CIS pointer */ PciEBAR0 = 0x30, /* expansion ROM base address */ PciMGNT = 0x3E, /* burst period length */ PciMLT = 0x3F, /* maximum latency between bursts */ }; enum { /* type 1 pre-defined header */ PciPBN = 0x18, /* primary bus number */ PciSBN = 0x19, /* secondary bus number */ PciUBN = 0x1A, /* subordinate bus number */ PciSLTR = 0x1B, /* secondary latency timer */ PciIBR = 0x1C, /* I/O base */ PciILR = 0x1D, /* I/O limit */ PciSPSR = 0x1E, /* secondary status */ PciMBR = 0x20, /* memory base */ PciMLR = 0x22, /* memory limit */ PciPMBR = 0x24, /* prefetchable memory base */ PciPMLR = 0x26, /* prefetchable memory limit */ PciPUBR = 0x28, /* prefetchable base upper 32 bits */ PciPULR = 0x2C, /* prefetchable limit upper 32 bits */ PciIUBR = 0x30, /* I/O base upper 16 bits */ PciIULR = 0x32, /* I/O limit upper 16 bits */ PciEBAR1 = 0x28, /* expansion ROM base address */ PciBCR = 0x3E, /* bridge control register */ }; typedef struct Pcidev Pcidev; typedef struct Pcidev { int tbdf; /* type+bus+device+function */
1995/0517		ushort vid; /* vendor ID */ ushort did; /* device ID */ ushort command; ushort status; uchar rid; /* revision ID */ uchar loclass; /* specific register-level programming interface */ uchar subclass; uchar baseclass; uchar clsize; /* cache line size */ uchar latency; /* latency timer */ uchar header; /* header type */ uchar bist; /* built-in self-test */ ulong baseaddr[6]; /* memory or I/O base address registers */ ulong reserved28[2]; ulong romaddr; /* expansion ROM base address */ ulong reserved34[2]; uchar irq; /* interrupt line */ uchar irp; /* interrupt pin */ uchar mingnt; /* burst period length */ uchar maxlat; /* maximum latency between bursts */ } PCIcfg;
1997/0327		ulong bar[2]; /* base address */ uchar intl; /* interrupt line */ Pcidev* next; /* next device on this bno */ } Pcidev; /* * PCMCIA support code. */ /* * Map between ISA memory space and PCMCIA card memory space. */ struct PCMmap { ulong ca; /* card address */ ulong cea; /* card end address */ ulong isa; /* ISA address */ int len; /* length of the ISA area */ int attr; /* attribute memory */ int ref; };