1998/0401/pc/mp.c (diff list | history)

1998/0320/sys/src/9/pc/mp.c:4,9 – 1998/0401/sys/src/9/pc/mp.c:4,10 (short | long | prev | next)
Add MTRR register support. Add NMI handler for debugging. The NMI handler prints the CPUs current PC. rsc Fri Mar 4 12:44:25 2005
1997/0327		#include "dat.h" #include "fns.h" #include "io.h"
1998/0401		#include "ureg.h"
1997/0327		#include "mp.h" #include "apbootstrap.h"
1998/0320/sys/src/9/pc/mp.c:287,292 – 1998/0401/sys/src/9/pc/mp.c:288,345
1997/0327		return v; }
1998/0401		static void checkmtrr(void) { int i, vcnt; Mach *mach0; /* * If there are MTRR registers, snarf them for validation. */ if(!(m->cpuiddx & 0x1000)) return; rdmsr(0x0FE, &m->mtrrcap); rdmsr(0x2FF, &m->mtrrdef); if(m->mtrrcap & 0x0100){ rdmsr(0x250, &m->mtrrfix[0]); rdmsr(0x258, &m->mtrrfix[1]); rdmsr(0x259, &m->mtrrfix[2]); for(i = 0; i < 8; i++) rdmsr(0x268+i, &m->mtrrfix[(i+3)]); } vcnt = m->mtrrcap & 0x00FF; if(vcnt > nelem(m->mtrrvar)) vcnt = nelem(m->mtrrvar); for(i = 0; i < vcnt; i++) rdmsr(0x200+i, &m->mtrrvar[i]); /* * If not the bootstrap processor, compare. */ if(m->machno == 0) return; mach0 = MACHP(0); if(mach0->mtrrcap != m->mtrrcap) print("mtrrcap%d: %lluX %lluX\n", m->machno, mach0->mtrrcap, m->mtrrcap); if(mach0->mtrrdef != m->mtrrdef) print("mtrrdef%d: %lluX %lluX\n", m->machno, mach0->mtrrdef, m->mtrrdef); for(i = 0; i < 11; i++){ if(mach0->mtrrfix[i] != m->mtrrfix[i]) print("mtrrfix%d: i%d: %lluX %lluX\n", m->machno, i, mach0->mtrrfix[i], m->mtrrfix[i]); } for(i = 0; i < vcnt; i++){ if(mach0->mtrrvar[i] != m->mtrrvar[i]) print("mtrrvar%d: i%d: %lluX %lluX\n", m->machno, i, mach0->mtrrvar[i], m->mtrrvar[i]); } }
1997/0327		#define PDX(va) ((((ulong)(va))>>22) & 0x03FF) #define PTX(va) ((((ulong)(va))>>12) & 0x03FF)
1998/0320/sys/src/9/pc/mp.c:301,306 – 1998/0401/sys/src/9/pc/mp.c:354,360
1997/0327		cpuidentify(); cpuidprint();
1998/0401		checkmtrr();
1997/0327		lock(&mprdthilock); mprdthi |= (1<<apic->apicno)<<24;
1998/0320/sys/src/9/pc/mp.c:392,397 – 1998/0401/sys/src/9/pc/mp.c:446,466
1997/0327		nvramwrite(0x0F, 0x00); }
1998/0401		static void senddbgnmi(void) { /* * NMI all excluding self. */ lapicicrw(0, 0x000C0000|ApicNMI); } static void mpdbg(Ureg* ureg, void*) { iprint("MPDBG: cpu%d: PC 0x%uX\n", m->machno, ureg->pc); }
1997/0327		void mpinit(void) {
1998/0320/sys/src/9/pc/mp.c:482,487 – 1998/0401/sys/src/9/pc/mp.c:551,558
1997/0405		intrenable(VectorSPURIOUS, lapicspurious, 0, BUSUNKNOWN); lapiconline(clkin);
1997/0327
1998/0401		checkmtrr();
1997/0405		/* * Initialise the application processors. */
1998/0320/sys/src/9/pc/mp.c:493,502 – 1998/0401/sys/src/9/pc/mp.c:564,576
1997/0327		/* * Remember to set conf.copymode here if nmach > 1. * Look for an ExtINT line and enable it.
1998/0401		* Should look for an ExtINT line and enable it.
1997/0327		*/ if(conf.nmach > 1) conf.copymode = 1;
1998/0401		consdebug = senddbgnmi; intrenable(VectorNMI, mpdbg, 0, BUSUNKNOWN);
1997/0327		} static int
1998/0320/sys/src/9/pc/mp.c:624,629 – 1998/0401/sys/src/9/pc/mp.c:698,705
1997/0327		void mpshutdown(void) {
1998/0401		int apicno, machno;
1997/0327		/* * To be done... */
1998/0320/sys/src/9/pc/mp.c:639,644 – 1998/0401/sys/src/9/pc/mp.c:715,728
1997/0327		} print("apshutdown: active = 0x%2.2uX\n", active.machs);
1998/0401		if(active.machs){ for(machno = 1; machno < conf.nmach; machno++){ if(!(active.machs & (1<<machno))) continue; apicno = machno2apicno[machno]; lapicicrw(1<<apicno, ApicNMI); } }
1997/0327		delay(1000); splhi();