1998/0401/pc/trap.c (diff list | history)

1998/0320/sys/src/9/pc/trap.c:26,34 – 1998/0401/sys/src/9/pc/trap.c:26,32 (short | long | prev | next)
Bug fix?: disable interrupts at start of system call, add preemptive scheduling, and more. Comment-out code differently. Use vlong with rdmsr. Add preemptive scheduling. Tweak NMI handler that parks non-0 CPUs — for debugging. rsc Fri Mar 4 12:44:25 2005
1997/0327		ctl = xalloc(sizeof(Irqctl));
1998/0320		if(v >= VectorINTR && arch->intrenable(v, tbdf, ctl) == -1){
1997/0327		unlock(&irqctllock); /* print("intrenable: didn't find v %d, tbdf 0x%uX\n", v, tbdf); */
1998/0401		//print("intrenable: didn't find v %d, tbdf 0x%uX\n", v, tbdf);
1997/0327		xfree(ctl); return; }
1998/0320/sys/src/9/pc/trap.c:77,83 – 1998/0401/sys/src/9/pc/trap.c:75,81
1997/1101		break; case VectorSYSCALL: d1 |= SEGPL(3)|SEGTG;
1998/0401		d1 |= SEGPL(3)|SEGIG;
1997/1101		break; default:
1998/0320/sys/src/9/pc/trap.c:157,162 – 1998/0401/sys/src/9/pc/trap.c:155,165
1993/0224
1997/0327		if(ctl->eoi) ctl->eoi(v);
1998/0401		/* preemptive scheduling */ if(ctl->isintr && v != VectorTIMER && v != VectorCLOCK) if(up && up->state == Running && anyhigher()) sched();
1991/0731		}
1997/0327		else if(v <= 16 && user){ spllo();
1998/0320/sys/src/9/pc/trap.c:188,196 – 1998/0401/sys/src/9/pc/trap.c:191,201
1997/0327		} else{
1998/0320		if(v == VectorNMI){
1997/0405		if(m->machno != 0)
1998/0401		nmienable(); if(m->machno != 0){ print("cpu%d: PC %8.8uX\n", m->machno, ureg->pc);
1997/0405		for(;;);
1998/0320		//nmienable();
1998/0401		}
1997/0405		}
1997/0327		dumpregs(ureg); if(v < nelem(excname))
1998/0320/sys/src/9/pc/trap.c:230,236 – 1998/0401/sys/src/9/pc/trap.c:235,241
1997/0327		dumpregs(Ureg* ureg)
1993/0915		{
1994/0813		extern ulong etext;
1997/0327		ulong mca[2], mct[2];
1998/0401		vlong mca, mct;
1993/1113
1997/0327		dumpregs2(ureg);
1994/0813
1998/0320/sys/src/9/pc/trap.c:245,254 – 1998/0401/sys/src/9/pc/trap.c:250,258
1997/0327		if(m->cpuiddx & 0x9A){ print(" CR4 %8.8luX", getcr4()); if((m->cpuiddx & 0xA0) == 0xA0){ rdmsr(0x00, &mca[1], &mca[0]); rdmsr(0x01, &mct[1], &mct[0]); print("\n MCA %8.8luX:%8.8luX MCT %8.8luX", mca[1], mca[0], mct[0]);
1998/0401		rdmsr(0x00, &mca); rdmsr(0x01, &mct); print("\n MCA %8.8lluX MCT %8.8lluX", mca, mct);
1997/0327		} } print("\n ur %luX up %luX\n", ureg, up);
1998/0320/sys/src/9/pc/trap.c:353,363 – 1998/0401/sys/src/9/pc/trap.c:357,366
1997/1101		scallnr = ureg->ax; up->scallnr = scallnr; if(scallnr == RFORK && up->fpstate == FPactive){ splhi(); fpsave(&up->fpsave); up->fpstate = FPinactive; spllo();
1992/0805		}
1998/0401		spllo();
1994/0715
1997/0327		sp = ureg->usp;
1993/0915		up->nerrlab = 0;