1998/1114/pc/i8259.c (diff list | history)

pc/i8259.c on 1997/0327
1997/0327		#include "u.h" #include "../port/lib.h" #include "mem.h" #include "dat.h" #include "fns.h" #include "io.h" /* * 8259 interrupt controllers */ enum { Int0ctl= 0x20, /* control port (ICW1, OCW2, OCW3) */ Int0aux= 0x21, /* everything else (ICW2, ICW3, ICW4, OCW1) */ Int1ctl= 0xA0, /* control port */ Int1aux= 0xA1, /* everything else (ICW2, ICW3, ICW4, OCW1) */ Icw1= 0x10, /* select bit in ctl register */ Ocw2= 0x00, Ocw3= 0x08, EOI= 0x20, /* non-specific end of interrupt */ Elcr1= 0x4D0, /* Edge/Level Triggered Register */ Elcr2= 0x4D1, }; static int int0mask; /* interrupts enabled for first 8259 */ static int int1mask; /* interrupts enabled for second 8259 */
1998/1022		int elcr; /* mask of level-triggered interrupts */
1998/0910		static Lock i8259lock;
1997/0327		void i8259init(void) {
1998/1022		int x;
1997/0327
1998/0910		ilock(&i8259lock);
1997/0327		int0mask = 0xFF; int1mask = 0xFF; /* * Set up the first 8259 interrupt processor.
1998/0910		* Make 8259 interrupts start at CPU vector VectorPIC.
1997/0327		* Set the 8259 as master with edge triggered * input with fully nested interrupts. */ outb(Int0ctl, (1<<4)|(0<<3)|(1<<0)); /* ICW1 - master, edge triggered, ICW4 will be sent */ outb(Int0aux, VectorPIC); /* ICW2 - interrupt vector offset */ outb(Int0aux, 0x04); /* ICW3 - have slave on level 2 */ outb(Int0aux, 0x01); /* ICW4 - 8086 mode, not buffered */ /* * Set up the second 8259 interrupt processor. * Make 8259 interrupts start at CPU vector VectorPIC+8. * Set the 8259 as slave with edge triggered * input with fully nested interrupts. */ outb(Int1ctl, (1<<4)|(0<<3)|(1<<0)); /* ICW1 - master, edge triggered, ICW4 will be sent */ outb(Int1aux, VectorPIC+8); /* ICW2 - interrupt vector offset */ outb(Int1aux, 0x02); /* ICW3 - I am a slave on level 2 */ outb(Int1aux, 0x01); /* ICW4 - 8086 mode, not buffered */
1998/1114		outb(Int1aux, int1mask);
1997/0327		/* * pass #2 8259 interrupts to #1 */ int0mask &= ~0x04; outb(Int0aux, int0mask); /* * Set Ocw3 to return the ISR when ctl read. * After initialisation status read is set to IRR. * Read IRR first to possibly deassert an outstanding * interrupt. */ inb(Int0ctl); outb(Int0ctl, Ocw3|0x03); inb(Int1ctl); outb(Int1ctl, Ocw3|0x03); /* * Check for Edge/Level register. * This check may not work for all chipsets.
1998/1022		* First try a non-intrusive test - the bits for * IRQs 13, 8, 2, 1 and 0 must be edge (0). If * that's OK try a R/W test.
1997/0327		*/
1998/1022		x = (inb(Elcr2)<<8)|inb(Elcr1); if(!(x & 0x2107)){ outb(Elcr1, 0); if(inb(Elcr1) == 0){ outb(Elcr1, 0x20); if(inb(Elcr1) == 0x20) elcr = x; outb(Elcr1, x & 0xFF); //print("ELCR: %4.4uX\n", elcr); }
1997/0327		}
1998/0910		iunlock(&i8259lock);
1997/0327		} int
1998/0910		i8259isr(int vno)
1997/0327		{ int isr;
1998/0910		if(vno < VectorPIC || vno > VectorPIC+MaxIrqPIC) return 0;
1997/0327		/* * tell the 8259 that we're done with the * highest level interrupt (interrupts are still * off at this point) */
1998/0910		ilock(&i8259lock); isr = inb(Int0ctl); outb(Int0ctl, EOI); if(vno >= VectorPIC+8){ isr |= inb(Int1ctl)<<8; outb(Int1ctl, EOI);
1997/0327		}
1998/0910		iunlock(&i8259lock);
1997/0327
1998/0910		return isr & (1<<(vno-VectorPIC));
1997/0327		} int
1998/0910		i8259enable(Vctl* v)
1997/0327		{
1998/0910		int irq;
1997/0327		/*
1998/0910		* Given an IRQ, enable the corresponding interrupt in the i8259 * and return the vector to be used. The i8259 is set to use a fixed * range of vectors starting at VectorPIC.
1997/0327		*/
1998/0910		irq = v->irq; if(irq < 0 || irq > MaxIrqPIC){ print("i8259enable: irq %d out of range\n", irq); return -1; } ilock(&i8259lock); if(irq < 8){ int0mask &= ~(1<<irq);
1997/0327		outb(Int0aux, int0mask); } else{
1998/0910		int1mask &= ~(1<<(irq-8));
1997/0327		outb(Int1aux, int1mask); }
1998/0910		if(elcr & (1<<irq)) v->eoi = i8259isr;
1997/0327		else
1998/0910		v->isr = i8259isr; iunlock(&i8259lock);
1997/0327
1998/0910		return VectorPIC+irq;
1997/0327		}