1998/1125/pc/dma.c (diff list | history)

pc/dma.c on 1991/0803
1991/0803		#include "u.h"
1992/0321		#include "../port/lib.h"
1991/0803		#include "mem.h" #include "dat.h" #include "fns.h" typedef struct DMAport DMAport; typedef struct DMA DMA; typedef struct DMAxfer DMAxfer; enum { /* * the byte registers for DMA0 are all one byte apart */ Dma0= 0x00, Dma0status= Dma0+0x8, /* status port */ Dma0reset= Dma0+0xD, /* reset port */ /* * the byte registers for DMA1 are all two bytes apart (why?) */ Dma1= 0xC0, Dma1status= Dma1+2*0x8, /* status port */ Dma1reset= Dma1+2*0xD, /* reset port */ }; /* * state of a dma transfer */ struct DMAxfer {
1996/0607		ulong bpa; /* bounce buffer physical address */ void* bva; /* bounce buffer virtual address */ void* va; /* virtual address destination/src */
1991/0803		long len; /* bytes to be transferred */ int isread; }; /* * the dma controllers. the first half of this structure specifies * the I/O ports used by the DMA controllers. */ struct DMAport { uchar addr[4]; /* current address (4 channels) */ uchar count[4]; /* current count (4 channels) */ uchar page[4]; /* page registers (4 channels) */ uchar cmd; /* command status register */ uchar req; /* request registers */ uchar sbm; /* single bit mask register */ uchar mode; /* mode register */ uchar cbp; /* clear byte pointer */ uchar mc; /* master clear */ uchar cmask; /* clear mask register */ uchar wam; /* write all mask register bit */ }; struct DMA { DMAport;
1995/0214		int shift;
1991/0803		Lock; DMAxfer x[4]; }; DMA dma[2] = { { 0x00, 0x02, 0x04, 0x06, 0x01, 0x03, 0x05, 0x07, 0x87, 0x83, 0x81, 0x82,
1995/0214		0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0 }, { 0xc0, 0xc4, 0xc8, 0xcc, 0xc2, 0xc6, 0xca, 0xce, 0x8f, 0x8b, 0x89, 0x8a, 0xd0, 0xd2, 0xd4, 0xd6, 0xd8, 0xda, 0xdc, 0xde, 1 },
1991/0803		}; /*
1997/0404		* DMA must be in the first 16MB. This gets called early by the * initialisation routines of any devices which require DMA to ensure * the allocated bounce buffers are below the 16MB limit.
1993/0915		*/ void
1997/0404		dmainit(int chan)
1993/0915		{ DMA *dp; DMAxfer *xp;
1997/0404		ulong v;
1993/0915
1997/0404		dp = &dma[(chan>>2)&1]; chan = chan & 3; xp = &dp->x[chan]; if(xp->bva != nil) return; v = (ulong)xalloc(BY2PG+BY2PG); if(v == 0 || PADDR(v) >= 16*MB){ print("dmainit: chan %d: 0x%luX out of range\n", chan, v); xfree((void*)v); v = 0;
1993/0915		}
1997/0404		xp->bva = (void*)ROUND(v, BY2PG); xp->bpa = PADDR(xp->bva); xp->len = 0; xp->isread = 0;
1993/0915		} /*
1991/0803		* setup a dma transfer. if the destination is not in kernel * memory, allocate a page for the transfer. * * we assume BIOS has set up the command register before we * are booted. * * return the updated transfer length (we can't transfer across 64k * boundaries) */ long dmasetup(int chan, void *va, long len, int isread) { DMA *dp; ulong pa; uchar mode;
1996/0607		DMAxfer *xp;
1991/0803		dp = &dma[(chan>>2)&1]; chan = chan & 3; xp = &dp->x[chan]; /*
1993/0915		* if this isn't kernel memory or crossing 64k boundary or above 16 meg * use the allocated low memory page.
1991/0803		*/
1993/0915		pa = PADDR(va);
1992/1013		if((((ulong)va)&0xF0000000) != KZERO
1993/0915		|| (pa&0xFFFF0000) != ((pa+len)&0xFFFF0000)
1998/1125		|| pa >= 16*MB) {
1997/0404		if(xp->bva == nil) return -1;
1991/0803		if(len > BY2PG) len = BY2PG; if(!isread)
1996/0607		memmove(xp->bva, va, len);
1991/0803		xp->va = va; xp->len = len; xp->isread = isread;
1996/0607		pa = xp->bpa; } else
1991/0925		xp->len = 0;
1991/0803		/* * this setup must be atomic */
1995/0214		ilock(dp);
1991/0803		mode = (isread ? 0x44 : 0x48) | chan;
1996/0607		outb(dp->mode, mode); /* single mode dma (give CPU a chance at mem) */
1991/0803		outb(dp->page[chan], pa>>16);
1995/0214		outb(dp->cbp, 0); /* set count & address to their first byte */ outb(dp->addr[chan], pa>>dp->shift); /* set address */ outb(dp->addr[chan], pa>>(8+dp->shift)); outb(dp->count[chan], (len>>dp->shift)-1); /* set count */ outb(dp->count[chan], ((len>>dp->shift)-1)>>8);
1991/0803		outb(dp->sbm, chan); /* enable the channel */
1995/0214		iunlock(dp);
1991/0803		return len; }
1995/0502		int dmadone(int chan) { DMA *dp; dp = &dma[(chan>>2)&1]; chan = chan & 3; return inb(dp->cmd) & (1<<chan); }
1991/0803		/* * this must be called after a dma has been completed. * * if a page has been allocated for the dma, * copy the data into the actual destination * and free the page. */ void dmaend(int chan) { DMA *dp; DMAxfer *xp; dp = &dma[(chan>>2)&1]; chan = chan & 3; /* * disable the channel */
1995/0214		ilock(dp);
1991/0803		outb(dp->sbm, 4|chan);
1995/0214		iunlock(dp);
1991/0803		xp = &dp->x[chan];
1994/1206		if(xp->len == 0 || !xp->isread)
1991/0803		return; /* * copy out of temporary page */
1996/0607		memmove(xp->va, xp->bva, xp->len);
1991/0925		xp->len = 0;
1995/0701		}
1997/0404		/*
1997/0327		int dmacount(int chan) { int retval; DMA *dp; dp = &dma[(chan>>2)&1]; outb(dp->cbp, 0); retval = inb(dp->count[chan]); retval |= inb(dp->count[chan]) << 8; return((retval<<dp->shift)+1); }
1997/0404		*/