1999/0301/pc/i8259.c (diff list | history)

1998/1114/sys/src/9/pc/i8259.c:25,34 – 1999/0301/sys/src/9/pc/i8259.c:25,33 (short | long | prev | next)
replace int0mask, int1mask with i8259mask. replace elcr with i8259elcr. check for shared non-level-triggered interrupts. rsc Fri Mar 4 12:44:25 2005
1997/0327		Elcr2= 0x4D1, }; static int int0mask; /* interrupts enabled for first 8259 */ static int int1mask; /* interrupts enabled for second 8259 */
1998/1022		int elcr; /* mask of level-triggered interrupts */
1998/0910		static Lock i8259lock;
1999/0301		static int i8259mask = 0xFFFF; /* disabled interrupts */ int i8259elcr; /* mask of level-triggered interrupts */
1997/0327		void i8259init(void)
1998/1114/sys/src/9/pc/i8259.c:36,43 – 1999/0301/sys/src/9/pc/i8259.c:35,40
1998/1022		int x;
1997/0327
1998/0910		ilock(&i8259lock);
1997/0327		int0mask = 0xFF; int1mask = 0xFF; /* * Set up the first 8259 interrupt processor.
1998/1114/sys/src/9/pc/i8259.c:62,74 – 1999/0301/sys/src/9/pc/i8259.c:59,71
1997/0327		outb(Int1aux, VectorPIC+8); /* ICW2 - interrupt vector offset */ outb(Int1aux, 0x02); /* ICW3 - I am a slave on level 2 */ outb(Int1aux, 0x01); /* ICW4 - 8086 mode, not buffered */
1998/1114		outb(Int1aux, int1mask);
1999/0301		outb(Int1aux, (i8259mask>>8) & 0xFF);
1997/0327		/* * pass #2 8259 interrupts to #1 */ int0mask &= ~0x04; outb(Int0aux, int0mask);
1999/0301		i8259mask &= ~0x04; outb(Int0aux, i8259mask & 0xFF);
1997/0327		/* * Set Ocw3 to return the ISR when ctl read.
1998/1114/sys/src/9/pc/i8259.c:94,102 – 1999/0301/sys/src/9/pc/i8259.c:91,99
1998/1022		if(inb(Elcr1) == 0){ outb(Elcr1, 0x20); if(inb(Elcr1) == 0x20) elcr = x;
1999/0301		i8259elcr = x;
1998/1022		outb(Elcr1, x & 0xFF); //print("ELCR: %4.4uX\n", elcr);
1999/0301		//print("ELCR: %4.4uX\n", i8259elcr);
1998/1022		}
1997/0327		}
1998/0910		iunlock(&i8259lock);
1998/1114/sys/src/9/pc/i8259.c:105,114 – 1999/0301/sys/src/9/pc/i8259.c:102,112
1997/0327		int
1998/0910		i8259isr(int vno)
1997/0327		{ int isr;
1999/0301		int irq, isr;
1997/0327
1998/0910		if(vno < VectorPIC || vno > VectorPIC+MaxIrqPIC) return 0;
1999/0301		irq = vno-VectorPIC;
1998/0910
1997/0327		/* * tell the 8259 that we're done with the
1998/1114/sys/src/9/pc/i8259.c:118,136 – 1999/0301/sys/src/9/pc/i8259.c:116,134
1998/0910		ilock(&i8259lock); isr = inb(Int0ctl); outb(Int0ctl, EOI); if(vno >= VectorPIC+8){
1999/0301		if(irq >= 8){
1998/0910		isr |= inb(Int1ctl)<<8; outb(Int1ctl, EOI);
1997/0327		}
1998/0910		iunlock(&i8259lock);
1997/0327
1998/0910		return isr & (1<<(vno-VectorPIC));
1999/0301		return isr & (1<<irq);
1997/0327		} int
1998/0910		i8259enable(Vctl* v)
1997/0327		{
1998/0910		int irq;
1999/0301		int irq, irqbit;
1997/0327		/*
1998/0910		* Given an IRQ, enable the corresponding interrupt in the i8259
1998/1114/sys/src/9/pc/i8259.c:142,159 – 1999/0301/sys/src/9/pc/i8259.c:140,160
1998/0910		print("i8259enable: irq %d out of range\n", irq); return -1; }
1999/0301		irqbit = 1<<irq;
1998/0910		ilock(&i8259lock); if(irq < 8){ int0mask &= ~(1<<irq);
1997/0327		outb(Int0aux, int0mask);
1999/0301		if(!(i8259mask & irqbit) && !(i8259elcr & irqbit)){ print("i8259enable: irq %d shared but not level\n", irq); iunlock(&i8259lock); return -1;
1997/0327		} else{
1998/0910		int1mask &= ~(1<<(irq-8));
1997/0327		outb(Int1aux, int1mask); }
1999/0301		i8259mask &= ~irqbit; if(irq < 8) outb(Int0aux, i8259mask & 0xFF); else outb(Int1aux, (i8259mask>>8) & 0xFF);
1997/0327
1998/0910		if(elcr & (1<<irq))
1999/0301		if(i8259elcr & irqbit)
1998/0910		v->eoi = i8259isr;
1997/0327		else
1998/0910		v->isr = i8259isr;