2000/0407/alphapc/vgas3.c (diff list | history)

2000/0401/sys/src/9/alphapc/vgas3.c:284,289 – 2000/0407/sys/src/9/alphapc/vgas3.c:284,491 (short | long | prev | next)
1999/0415		return 0; }
2000/0407		/* * The manual gives byte offsets, but we want ulong offsets, hence /4. */ enum { SrcBase = 0xA4D4/4, DstBase = 0xA4D8/4, Stride = 0xA4E4/4, FgrdData = 0xA4F4/4, WidthHeight = 0xA504/4, SrcXY = 0xA508/4, DestXY = 0xA50C/4, Command = 0xA500/4, SubStat = 0x8504/4, FifoStat = 0x850C/4, }; /* * Wait for writes to VGA memory via linear aperture to flush. */ enum {Maxloop = 1<<24}; struct { ulong linear; ulong fifo; ulong idle; } waitcount; static void waitforlinearfifo(VGAscr *scr) { ulong *mmio; long x; static ulong nwaitforlinearfifo; ulong mask, val; switch(scr->id){ default: panic("unknown scr->id in s3 waitforlinearfifo"); case 0xE131: /* ViRGE */ case 0xE13D: /* ViRGE/VX */ mask = 0x0F<<6; val = 0x08<<6; break; case 0xE110: /* ViRGE/GX2 */ mask = 0x1F<<6; val = 0x10<<6; break; } mmio = scr->mmio; x = 0; while((mmio[FifoStat]&mask) != val && x++ < Maxloop) waitcount.linear++; } static void waitforfifo(VGAscr *scr, int entries) { ulong *mmio; long x; static ulong nwaitforfifo; mmio = scr->mmio; x = 0; while((mmio[SubStat]&0x1F00) < ((entries+2)<<8) && x++ < Maxloop) waitcount.fifo++; } static void waitforidle(VGAscr *scr) { ulong *mmio; long x; mmio = scr->mmio; x = 0; while((mmio[SubStat]&0x3F00) != 0x3000 && x++ < Maxloop) waitcount.idle++; } static int hwscroll(VGAscr *scr, Rectangle r, Rectangle sr) { enum { Bitbltop = 0xCC }; /* copy source */ ulong *mmio; ulong cmd, stride; Point dp, sp; int did, d; d = scr->gscreen->depth; did = (d-8)/8; cmd = 0x00000020|(Bitbltop<<17)|(did<<2); stride = Dx(scr->gscreen->r)*d/8; if(r.min.x <= sr.min.x){ cmd |= 1<<25; dp.x = r.min.x; sp.x = sr.min.x; }else{ dp.x = r.max.x-1; sp.x = sr.max.x-1; } if(r.min.y <= sr.min.y){ cmd |= 1<<26; dp.y = r.min.y; sp.y = sr.min.y; }else{ dp.y = r.max.y-1; sp.y = sr.max.y-1; } mmio = scr->mmio; waitforlinearfifo(scr); waitforfifo(scr, 7); mmio[SrcBase] = scr->aperture; mmio[DstBase] = scr->aperture; mmio[Stride] = (stride<<16)|stride; mmio[WidthHeight] = ((Dx(r)-1)<<16)|Dy(r); mmio[SrcXY] = (sp.x<<16)|sp.y; mmio[DestXY] = (dp.x<<16)|dp.y; mmio[Command] = cmd; waitforidle(scr); return 1; } static int hwfill(VGAscr *scr, Rectangle r, ulong sval) { enum { Bitbltop = 0xCC }; /* copy source */ ulong *mmio; ulong cmd, stride; int did, d; d = scr->gscreen->depth; did = (d-8)/8; cmd = 0x16000120|(Bitbltop<<17)|(did<<2); stride = Dx(scr->gscreen->r)*d/8; mmio = scr->mmio; waitforlinearfifo(scr); waitforfifo(scr, 8); mmio[SrcBase] = scr->aperture; mmio[DstBase] = scr->aperture; mmio[DstBase] = scr->aperture; mmio[Stride] = (stride<<16)|stride; mmio[FgrdData] = sval; mmio[WidthHeight] = ((Dx(r)-1)<<16)|Dy(r); mmio[DestXY] = (r.min.x<<16)|r.min.y; mmio[Command] = cmd; waitforidle(scr); return 1; } enum { CursorSyncCtl = 0x0D, /* in Seqx */ VsyncHi = 0x80, VsyncLo = 0x40, HsyncHi = 0x20, HsyncLo = 0x10, }; static void s3blank(int blank) { uchar x; x = vgaxi(Seqx, CursorSyncCtl); x &= ~0xF0; if(blank) x |= VsyncLo | HsyncLo; vgaxo(Seqx, CursorSyncCtl, x); } static void s3drawinit(VGAscr *scr) { ulong id; id = (vgaxi(Crtx, 0x30)<<8)|vgaxi(Crtx, 0x2E); scr->id = id; /* * It's highly likely that other ViRGEs will work without * change to the driver, with the exception of the size of * the linear aperture memory write FIFO. Since we don't * know that size, I'm not turning them on. See waitforlinearfifo * above. */ switch(id){ case 0xE131: /* ViRGE */ case 0xE13D: /* ViRGE/VX */ case 0xE110: /* ViRGE/GX2 */ scr->mmio = (ulong*)(scr->pciaddr+0x1000000); /* * Untested on the Alpha. */ /* scr->fill = hwfill; scr->scroll = hwscroll; */ /* scr->blank = hwblank; */ } }
1999/0415		VGAdev vgas3dev = { "s3",
2000/0401/sys/src/9/alphapc/vgas3.c:291,296 – 2000/0407/sys/src/9/alphapc/vgas3.c:493,499
1999/0415		0, s3page, s3linear,
2000/0407		s3drawinit,
1999/0415		}; VGAcur vgas3cur = {