2000/0515/alphapc/io.h (diff list | history)

2000/0515/sys/src/9/alphapc/io.h:1,181 – 2001/0727/sys/src/9/alphapc/io.h:1,175 (short | long | prev)
1999/0415		enum { Uart0 = 0x3F8, Uart1 = 0x2F8, UartFREQ = 1843200, };                  enum { IrqCLOCK = 0, IrqKBD = 1, IrqUART1 = 3, IrqUART0 = 4, IrqPCMCIA = 5, IrqFLOPPY = 6, IrqLPT = 7, IrqIRQ7 = 7, IrqAUX = 12, /* PS/2 port */ IrqIRQ13 = 13, /* coprocessor on 386 */ IrqATA0 = 14,
2000/0407		IrqATA1 = 15,
1999/0415		MaxIrqPIC = 15,
2000/0401		VectorPIC = 64, MaxVectorPIC = VectorPIC+MaxIrqPIC,
1999/0415		VectorPCI = 16, /* PCI bus (PLD) */ };
2000/0401		typedef struct Vctl { Vctl* next; /* handlers on this vector */
1999/0415
2000/0401		char name[NAMELEN]; /* of driver */
2001/0727		char name[KNAMELEN]; /* of driver */
2000/0401		int isintr; /* interrupt or fault/trap */ int irq; int tbdf;
1999/0415		int (*isr)(int); /* get isr bit for this irq */ int (*eoi)(int); /* eoi */
2000/0401		void (*f)(Ureg*, void*); /* handler to call */ void* a; /* argument to call it with */ } Vctl;
1999/0415		enum { BusCBUS = 0, /* Corollary CBUS */ BusCBUSII, /* Corollary CBUS II */ BusEISA, /* Extended ISA */ BusFUTURE, /* IEEE Futurebus */ BusINTERN, /* Internal bus */ BusISA, /* Industry Standard Architecture */ BusMBI, /* Multibus I */ BusMBII, /* Multibus II */ BusMCA, /* Micro Channel Architecture */ BusMPI, /* MPI */ BusMPSA, /* MPSA */ BusNUBUS, /* Apple Macintosh NuBus */ BusPCI, /* Peripheral Component Interconnect */ BusPCMCIA, /* PC Memory Card International Association */ BusTC, /* DEC TurboChannel */ BusVL, /* VESA Local bus */ BusVME, /* VMEbus */ BusXPRESS, /* Express System Bus */ }; #define MKBUS(t,b,d,f) (((t)<<24)|(((b)&0xFF)<<16)|(((d)&0x1F)<<11)|(((f)&0x07)<<8)) #define BUSFNO(tbdf) (((tbdf)>>8)&0x07) #define BUSDNO(tbdf) (((tbdf)>>11)&0x1F) #define BUSBNO(tbdf) (((tbdf)>>16)&0xFF) #define BUSTYPE(tbdf) ((tbdf)>>24) #define BUSDF(tbdf) ((tbdf)&0x000FF00) #define BUSBDF(tbdf) ((tbdf)&0x0FFFF00) #define BUSUNKNOWN (-1) enum { MaxEISA = 16, EISAconfig = 0xC80, }; /* * PCI support code. */ enum { /* type 0 and type 1 pre-defined header */ PciVID = 0x00, /* vendor ID */ PciDID = 0x02, /* device ID */ PciPCR = 0x04, /* command */ PciPSR = 0x06, /* status */ PciRID = 0x08, /* revision ID */ PciCCRp = 0x09, /* programming interface class code */ PciCCRu = 0x0A, /* sub-class code */ PciCCRb = 0x0B, /* base class code */ PciCLS = 0x0C, /* cache line size */ PciLTR = 0x0D, /* latency timer */ PciHDT = 0x0E, /* header type */ PciBST = 0x0F, /* BIST */ PciBAR0 = 0x10, /* base address */ PciBAR1 = 0x14,
2000/0401		PciROM = 0x30,
1999/0415		PciINTL = 0x3C, /* interrupt line */ PciINTP = 0x3D, /* interrupt pin */ }; enum { /* type 0 pre-defined header */ PciBAR2 = 0x18, PciBAR3 = 0x1C, PciBAR4 = 0x20, PciBAR5 = 0x24, PciCIS = 0x28, /* cardbus CIS pointer */ PciSVID = 0x2C, /* subsystem vendor ID */ PciSID = 0x2E, /* cardbus CIS pointer */ PciEBAR0 = 0x30, /* xpansion ROM base address */ PciMGNT = 0x3E, /* burst period length */ PciMLT = 0x3F, /* maximum latency between bursts */ }; enum { /* type 1 pre-defined header */ PciPBN = 0x18, /* primary bus number */ PciSBN = 0x19, /* secondary bus number */ PciUBN = 0x1A, /* subordinate bus number */ PciSLTR = 0x1B, /* secondary latency timer */ PciIBR = 0x1C, /* I/O base */ PciILR = 0x1D, /* I/O limit */ PciSPSR = 0x1E, /* secondary status */ PciMBR = 0x20, /* memory base */ PciMLR = 0x22, /* memory limit */ PciPMBR = 0x24, /* prefetchable memory base */ PciPMLR = 0x26, /* prefetchable memory limit */ PciPUBR = 0x28, /* prefetchable base upper 32 bits */ PciPULR = 0x2C, /* prefetchable limit upper 32 bits */ PciIUBR = 0x30, /* I/O base upper 16 bits */ PciIULR = 0x32, /* I/O limit upper 16 bits */ PciEBAR1 = 0x28, /* expansion ROM base address */ PciBCR = 0x3E, /* bridge control register */ }; typedef struct Pcidev Pcidev; typedef struct Pcidev {
2000/0515		int tbdf; /* type+bus+device+function */
1999/0415		ushort vid; /* vendor ID */ ushort did; /* device ID */
2000/0515		uchar rid; uchar ccrp; uchar ccru; uchar ccrb;
1999/0415		struct { ulong bar; /* base address */ int size;
1999/0507		} mem[6];
1999/0415		uchar intl; /* interrupt line */ Pcidev* list; Pcidev* link; /* next device on this bno */
2000/0515		Pcidev* bridge; /* down a bus */ struct { ulong bar; int size; } ioa, mema; ulong pcr;
1999/0415		};
2000/0515		#define PCIWINDOW 0x40000000 #define PCIWADDR(va) (PADDR(va)+PCIWINDOW) #define ISAWINDOW 0x00800000 #define ISAWADDR(va) (PADDR(va)+ISAWINDOW)
1999/0415		/* * PCMCIA support code. */ /* * Map between ISA memory space and PCMCIA card memory space. */ struct PCMmap { ulong ca; /* card address */ ulong cea; /* card end address */ ulong isa; /* ISA address */ int len; /* length of the ISA area */ int attr; /* attribute memory */ int ref; };