2000/0701/pc/i8253.c (diff list | history)

2000/0627/sys/src/9/pc/i8253.c:53,58 – 2000/0701/sys/src/9/pc/i8253.c:53,59 (short | long | prev | next)
2000/0623		static struct {
2000/0627		Lock;
2000/0701		int enabled;
2000/0627		int mode;
2000/0623		vlong when; /* next fastticks a clock interrupt should occur */
2000/0627		vlong cycwhen; /* next fastticks a cycintr happens; 0 == infinity */
2000/0627/sys/src/9/pc/i8253.c:198,203 – 2000/0701/sys/src/9/pc/i8253.c:199,210
2000/0627		} }
2000/0623
2000/0701		int havecycintr(void) { return i8253.enabled; }
2000/0627		void clockintrsched(void) {
2000/0627/sys/src/9/pc/i8253.c:204,212 – 2000/0701/sys/src/9/pc/i8253.c:211,221
2000/0627		vlong next; ilock(&i8253); next = cycintrnext(); if(next != i8253.cycwhen) clockintrsched0(next);
2000/0701		if(i8253.enabled){ next = cycintrnext(); if(next != i8253.cycwhen) clockintrsched0(next); }
2000/0627		iunlock(&i8253); }
2000/0627/sys/src/9/pc/i8253.c:233,238 – 2000/0701/sys/src/9/pc/i8253.c:242,248
2000/0623		i8253.when = fastticks(nil); i8253.fastperiod = (m->cpuhz + HZ/2) / HZ; i8253.fast2freq = (vlong)m->cpuhz * FreqMul / Freq;
2000/0701		i8253.enabled = 1;
2000/0621		intrenable(IrqCLOCK, clockintr0, 0, BUSUNKNOWN, "clock");
1997/0327		}
1998/0710