2000/0905/bitsy/l.s (diff list | history)

2000/0904/sys/src/9/bitsy/l.s:12,24 – 2000/0905/sys/src/9/bitsy/l.s:12,31 (short | long | prev | next)
2000/0901		MOVW $(PsrDirq|PsrDfiq|PsrMsvc), R1
2000/0831		MOVW R1, CPSR
2000/0901		/* turn on caches and write buffer */ MRC CpMMU, 0, R1, C(CpControl), C(0x0) ORR $(CpCdcache|CpCwb), R1 MCR CpMMU, 0, R1, C(CpControl), C(0x0)
2000/0905		/* flush TLB's */ MCR CpMMU, 0, R0, C(CpCacheFlush), C(0x0) /* drain prefetch */ MOVW R0,R0 MOVW R0,R0 MOVW R0,R0 MOVW R0,R0
2000/0901
2000/0902		/* turn off interrupts */ BL splhi(SB)
2000/0905		/* drain write buffer */ MCR CpMMU, 0, R0, C(CpCacheFlush), C(0x0), 4 /* disable the MMU */ MOVW $0x130, R1 MCR CpMMU, 0, R1, C(CpControl), C(0x0)
2000/0902
2000/0831		MOVW $(MACHADDR+BY2PG), R13 /* stack */ SUB $4, R13 /* link */