2000/0928/bitsy/mmu.c (diff list | history)

2000/0924/sys/src/9/bitsy/mmu.c:63,81 – 2000/0928/sys/src/9/bitsy/mmu.c:63,82 (short | long | prev | next)
2000/0905		{
2000/0906		ulong a, e; /* set up the domain register to cause all domains to obey pte access bits */ putdac(0x55555555);                  /* get a prototype level 1 page */
2000/0907		l1table = xspanalloc(BY2PG, 16*1024, 0); memset(l1table, 0, BY2PG);
2000/0906
2000/0907		/* direct map DRAM */ e = conf.base1 + BY2PG*conf.npage2;
2000/0928		e = conf.base1 + BY2PG*conf.npage1;
2000/0907		for(a = PHYSDRAM0; a < e; a += OneMeg) l1table[a>>20] = L1Section | L1KernelRW | L1Cached | L1Buffered | (a&L1SectBaseMask);
2000/0928		/* direct map devs */ for(a = REGZERO; a < REGTOP; a += OneMeg) l1table[a>>20] = L1Section | L1KernelRW | (a&L1SectBaseMask);
2000/0907		/* direct map zeros area */ for(a = PHYSNULL0; a < PHYSNULL0 + 128 * OneMeg; a += OneMeg) l1table[a>>20] = L1Section | L1KernelRW |
2000/0924/sys/src/9/bitsy/mmu.c:82,93 – 2000/0928/sys/src/9/bitsy/mmu.c:83,102
2000/0907		L1Cached | L1Buffered | (a&L1SectBaseMask); /* direct map flash */ for(a = PHYFLASH0; a < PHYFLASH0 + 128 * OneMeg; a += OneMeg)
2000/0928		for(a = PHYSFLASH0; a < PHYSFLASH0 + 128 * OneMeg; a += OneMeg)
2000/0907		l1table[a>>20] = L1Section | L1KernelRW | L1Cached | L1Buffered | (a&L1SectBaseMask); /* map the uart so that we can continue using iprint */ uart3regs = mapspecial(UART3REGS, 64);
2000/0928		// uart3regs = mapspecial(UART3REGS, 64); /* set up the domain register to cause all domains to obey pte access bits */ iprint("setting up domain access\n"); putdac(0x55555555); /* point to map */ iprint("setting tlb map %lux\n", (ulong)l1table); putttb((ulong)l1table);
2000/0907		} /*
2000/0924/sys/src/9/bitsy/mmu.c:97,103 – 2000/0928/sys/src/9/bitsy/mmu.c:106,112
2000/0924		mapspecial(ulong pa, int len)
2000/0907		{ ulong *t;
2000/0924		ulong va, i, base, end, off;
2000/0928		ulong va, i, base, end, off, entry;
2000/0924		int livelarge; ulong* rv;
2000/0907
2000/0924/sys/src/9/bitsy/mmu.c:127,133 – 2000/0928/sys/src/9/bitsy/mmu.c:136,142
2000/0924		/* create a page table and keep going */
2000/0907		t = xspanalloc(BY2PG, 1024, 0); memzero(t, BY2PG, 0);
2000/0928		memset(t, 0, BY2PG);
2000/0924		l1table[va>>20] = L1PageTable | L1Domain0 |
2000/0921		(((ulong)t) & L1PTBaseMask);
2000/0907		}