2000/0929/bitsy/mmu.c (diff list | history)

2000/0928/sys/src/9/bitsy/mmu.c:62,67 – 2000/0929/sys/src/9/bitsy/mmu.c:62,68 (short | long | prev | next)
2000/0905		mmuinit(void) {
2000/0906		ulong a, e;
2000/0929		ulong *t;
2000/0906		/* get a prototype level 1 page */
2000/0907		l1table = xspanalloc(BY2PG, 16*1024, 0);
2000/0928/sys/src/9/bitsy/mmu.c:70,102 – 2000/0929/sys/src/9/bitsy/mmu.c:71,109
2000/0907		/* direct map DRAM */
2000/0928		e = conf.base1 + BY2PG*conf.npage1;
2000/0907		for(a = PHYSDRAM0; a < e; a += OneMeg) l1table[a>>20] = L1Section | L1KernelRW | L1Cached | L1Buffered | (a&L1SectBaseMask);
2000/0929		l1table[a>>20] = L1Section | L1KernelRW | (a&L1SectBaseMask) | L1Cached | L1Buffered;
2000/0907
2000/0928		/* direct map devs */ for(a = REGZERO; a < REGTOP; a += OneMeg) l1table[a>>20] = L1Section | L1KernelRW | (a&L1SectBaseMask);
2000/0907		/* direct map zeros area */ for(a = PHYSNULL0; a < PHYSNULL0 + 128 * OneMeg; a += OneMeg) l1table[a>>20] = L1Section | L1KernelRW | L1Cached | L1Buffered | (a&L1SectBaseMask);
2000/0929		l1table[a>>20] = L1Section | L1KernelRW | (a&L1SectBaseMask);
2000/0907		/* direct map flash */
2000/0928		for(a = PHYSFLASH0; a < PHYSFLASH0 + 128 * OneMeg; a += OneMeg)
2000/0907		l1table[a>>20] = L1Section | L1KernelRW | L1Cached | L1Buffered | (a&L1SectBaseMask);
2000/0929		l1table[a>>20] = L1Section | L1KernelRW | (a&L1SectBaseMask) | L1Cached | L1Buffered;
2000/0907		/* map the uart so that we can continue using iprint */
2000/0928		// uart3regs = mapspecial(UART3REGS, 64);
2000/0929		/* map first page of DRAM also into 0xFFFF0000 for the interrupt vectors */ t = xspanalloc(BY2PG, 16*1024, 0); memset(t, 0, BY2PG); l1table[0xFFFF0000>>20] = L1PageTable | L1Domain0 | (((ulong)t) & L1PTBaseMask); t[0xF0000>>PGSHIFT] = L2SmallPage | L2KernelRW | PHYSDRAM0;
2000/0928		/* set up the domain register to cause all domains to obey pte access bits */ iprint("setting up domain access\n"); putdac(0x55555555);
2000/0929		putdac(0xFFFFFFFF);
2000/0928		/* point to map */ iprint("setting tlb map %lux\n", (ulong)l1table); putttb((ulong)l1table);
2000/0929		/* map the uart so that we can continue using iprint */ uart3regs = (Uartregs*)mapspecial(UART3REGS, 64); /* enable mmu, and make 0xFFFF0000 the virtual address of the exception vecs */ mmuenable(); iprint("uart3regs now at %lux\n", uart3regs);
2000/0907		} /*
2000/0928/sys/src/9/bitsy/mmu.c:121,146 – 2000/0929/sys/src/9/bitsy/mmu.c:128,162
2000/0924		} off = pa - base;
2000/0921
2000/0924		for(va = REGZERO; va < REGTOP && base >= end; va += OneMeg){ if((l1table[va>>20] & L1TypeMask) != L1PageTable){
2000/0929		for(va = REGZERO; va < REGTOP && base <= end; va += OneMeg){ switch(l1table[va>>20] & L1TypeMask){ default:
2000/0924		/* found unused entry on level 1 table */ if(livelarge){ if(rv == nil) rv = (ulong*)(va+i*BY2PG+off);
2000/0929		rv = (ulong*)(va+off);
2000/0924		l1table[va>>20] = L1Section | L1KernelRW | (base&L1SectBaseMask);
2000/0929		(base & L1SectBaseMask);
2000/0924		base += OneMeg; continue; }
2000/0929		} else {
2000/0924		/* create a page table and keep going */
2000/0907		t = xspanalloc(BY2PG, 1024, 0);
2000/0928		memset(t, 0, BY2PG);
2000/0924		l1table[va>>20] = L1PageTable | L1Domain0 |
2000/0921		(((ulong)t) & L1PTBaseMask);
2000/0929		/* create an L2 page table and keep going */ t = xspanalloc(BY2PG, 1024, 0); memset(t, 0, BY2PG); l1table[va>>20] = L1PageTable | L1Domain0 | (((ulong)t) & L1PTBaseMask); } break; case L1Section: continue; case L1PageTable: if(livelarge) continue; break;
2000/0907		}
2000/0924
2000/0929		/* here if we're using page maps instead of sections */
2000/0924		t = (ulong*)(l1table[va>>20] & L1PTBaseMask);
2000/0907		for(i = 0; i < OneMeg; i += BY2PG){
2000/0924		entry = t[i>>PGSHIFT];
2000/0928/sys/src/9/bitsy/mmu.c:148,154 – 2000/0929/sys/src/9/bitsy/mmu.c:164,170
2000/0924		/* found unused entry on level 2 table */ if((entry & L2TypeMask) != L2SmallPage){ if(rv == nil) rv = (ulong*)(va+i*BY2PG+off);
2000/0929		rv = (ulong*)(va+i+off);
2000/0924		t[i>>PGSHIFT] = L2SmallPage | L2KernelRW | (base & L2PageBaseMask); base += BY2PG;