2000/1007/bitsy/l.s (diff list | history)

2000/1002/sys/src/9/bitsy/l.s:10,18 – 2000/1007/sys/src/9/bitsy/l.s:10,22 (short | long | prev | next)
2000/0901		MOVW $(PsrDirq|PsrDfiq|PsrMsvc), R1
2000/0831		MOVW R1, CPSR
2000/0901
2000/0905		/* flush TLB's */ MCR CpMMU, 0, R0, C(CpCacheFlush), C(0x0) /* drain prefetch */
2000/1007		/* disable the MMU */ MOVW $0x130, R1 MCR CpMMU, 0, R1, C(CpControl), C(0x0) /* flush caches */ MCR CpMMU, 0, R0, C(CpCacheFlush), C(0x7), 0 /* drain prefetch */
2000/0905		MOVW R0,R0 MOVW R0,R0 MOVW R0,R0
2000/1002/sys/src/9/bitsy/l.s:19,30 – 2000/1007/sys/src/9/bitsy/l.s:23,30
2000/0905		MOVW R0,R0
2000/0901
2000/0905		/* drain write buffer */ MCR CpMMU, 0, R0, C(CpCacheFlush), C(0x0), 4
2000/1007		MCR CpMMU, 0, R0, C(CpCacheFlush), C(0xa), 4
2000/0905		/* disable the MMU */ MOVW $0x130, R1 MCR CpMMU, 0, R1, C(CpControl), C(0x0)
2000/0902
2000/0831		MOVW $(MACHADDR+BY2PG), R13 /* stack */ SUB $4, R13 /* link */ BL main(SB)
2000/1002/sys/src/9/bitsy/l.s:36,47 – 2000/1007/sys/src/9/bitsy/l.s:36,47
2000/0831
2000/0901		/* flush tlb's */ TEXT flushmmu(SB), $-4 MCR CpMMU, 0, R0, C(CpTLBFlush), C(0x0)
2000/1007		MCR CpMMU, 0, R0, C(CpTLBFlush), C(0x7)
2000/0831		RET
2000/0901		/* flush instruction cache */ TEXT flushicache(SB), $-4 MCR CpMMU, 0, R0, C(CpCacheFlush), C(0x0)
2000/1007		MCR CpMMU, 0, R0, C(CpCacheFlush), C(0x5), 0
2000/0901		/* drain prefetch */ MOVW R0,R0 MOVW R0,R0
2000/1002/sys/src/9/bitsy/l.s:51,62 – 2000/1007/sys/src/9/bitsy/l.s:51,62
2000/0831
2000/0901		/* flush data cache */ TEXT flushdcache(SB), $-4 MCR CpMMU, 0, R0, C(CpCacheFlush), C(0x0)
2000/1007		MCR CpMMU, 0, R0, C(CpCacheFlush), C(0x6), 0
2000/0831		RET
2000/0901		/* flush i and d caches */ TEXT flushcache(SB), $-4 MCR CpMMU, 0, R0, C(CpCacheFlush), C(0x0)
2000/1007		MCR CpMMU, 0, R0, C(CpCacheFlush), C(0x7), 0
2000/0901		/* drain prefetch */ MOVW R0,R0 MOVW R0,R0
2000/1002/sys/src/9/bitsy/l.s:66,72 – 2000/1007/sys/src/9/bitsy/l.s:66,72
2000/0831
2000/0901		/* drain write buffer */
2000/0929		TEXT wbflush(SB), $-4
2000/0901		MCR CpMMU, 0, R0, C(CpCacheFlush), C(0x0), 4
2000/1007		MCR CpMMU, 0, R0, C(CpCacheFlush), C(0xa), 4
2000/0831		RET
2000/0901		/* return cpu id */
2000/1002/sys/src/9/bitsy/l.s:90,100 – 2000/1007/sys/src/9/bitsy/l.s:90,100
2000/0929		RET
2000/0906
2000/0929		/* * enable mmu, i and d caches, and exception vectors at 0xffff0000
2000/1007		* enable mmu, i and d caches
2000/0929		*/ TEXT mmuenable(SB), $-4 MRC CpMMU, 0, R0, C(CpControl), C(0x0) ORR $(CpCmmuena|CpCdcache|CpCicache|CpCvivec), R0
2000/1007		ORR $(CpCmmuena|CpCdcache|CpCicache), R0
2000/0929		MCR CpMMU, 0, R0, C(CpControl), C(0x0) RET
2000/1002/sys/src/9/bitsy/l.s:104,109 – 2000/1007/sys/src/9/bitsy/l.s:104,123
2000/0929		MCR CpMMU, 0, R0, C(CpControl), C(0x0) RET
2000/1007		/* * use exception vectors at 0xffff0000 */ TEXT mappedIvecEnable(SB), $-4 MRC CpMMU, 0, R0, C(CpControl), C(0x0) ORR $(CpCvivec), R0 MCR CpMMU, 0, R0, C(CpControl), C(0x0) RET TEXT mappedIvecDisable(SB), $-4 MRC CpMMU, 0, R0, C(CpControl), C(0x0) BIC $(CpCvivec), R0 MCR CpMMU, 0, R0, C(CpControl), C(0x0) RET
2000/0906		/* set the translation table base */ TEXT putdac(SB), $-4 MCR CpMMU, 0, R0, C(CpDAC), C(0x0)
2000/1002/sys/src/9/bitsy/l.s:134,156 – 2000/1007/sys/src/9/bitsy/l.s:148,173
2000/0904		/* * exception vectors, copied by trapinit() to somewhere useful */
2000/0929		TEXT exceptionvectors(SB), $-4
2000/0904		MOVW 0x18(R15), R15 /* reset */ MOVW 0x18(R15), R15 /* undefined */ MOVW 0x18(R15), R15 /* SWI */ MOVW 0x18(R15), R15 /* prefetch abort */ MOVW 0x18(R15), R15 /* data abort */ MOVW 0x18(R15), R15 /* reserved */ MOVW 0x18(R15), R15 /* IRQ */ MOVW 0x18(R15), R15 /* FIQ */
2000/1001		WORD $_vrst(SB) /* reset, in svc mode already */
2000/0904		WORD $_vund(SB) /* undefined, switch to svc mode */ WORD $_vsvc(SB) /* swi, in svc mode already */
2000/1001		WORD $_vabt(SB) /* prefetch abort, switch to svc mode */ WORD $_vabt(SB) /* data abort, switch to svc mode */ WORD $_vrst(SB) /* reserved, shouldn't happen */
2000/0904		WORD $_virq(SB) /* IRQ, switch to svc mode */ WORD $_vfiq(SB) /* FIQ, switch to svc mode */
2000/1007		TEXT vectors(SB), $-4 MOVW 0x18(R15), R15 /* reset */ MOVW 0x18(R15), R15 /* undefined */ MOVW 0x18(R15), R15 /* SWI */ MOVW 0x18(R15), R15 /* prefetch abort */ MOVW 0x18(R15), R15 /* data abort */ MOVW 0x18(R15), R15 /* reserved */ MOVW 0x18(R15), R15 /* IRQ */ MOVW 0x18(R15), R15 /* FIQ */ TEXT vtable(SB), $-4 WORD $_vsvc(SB) /* reset, in svc mode already */ WORD $_vund(SB) /* undefined, switch to svc mode */ WORD $_vsvc(SB) /* swi, in svc mode already */ WORD $_vabt(SB) /* prefetch abort, switch to svc mode */ WORD $_vabt(SB) /* data abort, switch to svc mode */ WORD $_vsvc(SB) /* reserved */ WORD $_virq(SB) /* IRQ, switch to svc mode */ WORD $_vfiq(SB) /* FIQ, switch to svc mode */
2000/0831
2000/1001		TEXT _vrst(SB), $-4
2000/1002		BL reset(SB)