2000/1007/bitsy/mmu.c (diff list | history)

2000/1006/sys/src/9/bitsy/mmu.c:54,59 – 2000/1007/sys/src/9/bitsy/mmu.c:54,60 (short | long | prev | next)
2000/0906
2000/0907		ulong *l1table;
2000/0906
2000/1007
2000/0906		/* * We map all of memory, flash, and the zeros area with sections. * Special use space is mapped on the fly with regmap.
2000/1006/sys/src/9/bitsy/mmu.c:65,72 – 2000/1007/sys/src/9/bitsy/mmu.c:66,73
2000/0929		ulong *t;
2000/0906		/* get a prototype level 1 page */
2000/0907		l1table = xspanalloc(BY2PG, 16*1024, 0); memset(l1table, 0, BY2PG);
2000/1007		l1table = xspanalloc(16*1024, 16*1024, 0); memset(l1table, 0, 16*1024);
2000/0906
2000/0907		/* direct map DRAM */
2000/0928		e = conf.base1 + BY2PG*conf.npage1;
2000/1006/sys/src/9/bitsy/mmu.c:83,93 – 2000/1007/sys/src/9/bitsy/mmu.c:84,97
2000/0929		l1table[a>>20] = L1Section | L1KernelRW | (a&L1SectBaseMask) | L1Cached | L1Buffered;
2000/0907
2000/0929		/* map first page of DRAM also into 0xFFFF0000 for the interrupt vectors */ t = xspanalloc(BY2PG, 16*1024, 0);
2000/1007		/* * double map start of ram to exception vectors */ a = EVECTORS; t = xspanalloc(BY2PG, 1024, 0);
2000/0929		memset(t, 0, BY2PG); l1table[0xFFFF0000>>20] = L1PageTable | L1Domain0 | (((ulong)t) & L1PTBaseMask); t[0xF0000>>PGSHIFT] = L2SmallPage | L2KernelRW | PHYSDRAM0;
2000/1007		l1table[a>>20] = L1PageTable | L1Domain0 | (((ulong)t) & L1PTBaseMask); t[(a&0xfffff)>>PGSHIFT] = L2SmallPage | L2KernelRW | (PHYSDRAM0 & L2PageBaseMask);
2000/0928		/* set up the domain register to cause all domains to obey pte access bits */ iprint("setting up domain access\n");
2000/1006/sys/src/9/bitsy/mmu.c:97,103 – 2000/1007/sys/src/9/bitsy/mmu.c:101,110
2000/0928		iprint("setting tlb map %lux\n", (ulong)l1table); putttb((ulong)l1table);
2000/0929		/* enable mmu, and make 0xFFFF0000 the virtual address of the exception vecs */
2000/1007		/* enable mmu */ wbflush(); flushcache(); flushmmu();
2000/0929		mmuenable();
2000/0907		}