2000/1018/bitsy/l.s (diff list | history)

2000/1015/sys/src/9/bitsy/l.s:39,55 – 2000/1018/sys/src/9/bitsy/l.s:39,60 (short | long | prev | next)
2000/1007		MCR CpMMU, 0, R0, C(CpTLBFlush), C(0x7)
2000/0831		RET
2000/1018		/* flush tlb's */ TEXT mmuinvalidateaddr(SB), $-4 MCR CpMMU, 0, R0, C(CpTLBFlush), C(0x6), 1 RET
2000/1015		/* write back and invalidate i and d caches */ TEXT cacheflush(SB), $-4
2000/1010		/* write back any dirty data */ MOVW $0xe0000000,R0 ADD $(8*1024),R0,R1 _wbloop: MOVW.W 32(R0),R2
2000/1018		_cfloop: MOVW.P 32(R0),R2
2000/1010		CMP R0,R1 BNE _wbloop
2000/1018		BNE _cfloop
2000/1010
2000/1015		/* drain write buffer and flush i&d cache contents */
2000/1018		/* drain write buffer and invalidate i&d cache contents */
2000/1015		MCR CpMMU, 0, R0, C(CpCacheFlush), C(0xa), 4
2000/1007		MCR CpMMU, 0, R0, C(CpCacheFlush), C(0x7), 0
2000/1010
2000/1015/sys/src/9/bitsy/l.s:60,72 – 2000/1018/sys/src/9/bitsy/l.s:65,116
2000/0901		MOVW R0,R0
2000/1014		RET
2000/0831
2000/1014		/* clean a single virtual address */
2000/1015		TEXT cacheflushaddr(SB), $-4
2000/1018		/* write back and invalidate i and d caches */ TEXT cachewb(SB), $-4 /* write back any dirty data */ MOVW $0xe0000000,R0 ADD $(8*1024),R0,R1 _cwbloop: MOVW.P 32(R0),R2 CMP R0,R1 BNE _cfloop /* drain write buffer */ MCR CpMMU, 0, R0, C(CpCacheFlush), C(0xa), 4 RET /* write back a single cache line */ TEXT cachewbaddr(SB), $-4 BIC $31,R0
2000/1014		MCR CpMMU, 0, R0, C(CpCacheFlush), C(0xa), 1
2000/1018		B _wbflush /* write back a region of cache lines */ TEXT cachewbregion(SB), $-4 MOVW 4(FP),R1 BIC $31,R0 ADD R0,R1 ADD $32,R1 _cfrloop: MCR CpMMU, 0, R0, C(CpCacheFlush), C(0xa), 1 ADD $32,R0 CMP.S R0,R1 BNE _cfrloop B _wbflush /* invalidate the dcache */ TEXT dcacheinvalidate(SB), $-4 MCR CpMMU, 0, R0, C(CpCacheFlush), C(0x6)
2000/1014		RET
2000/1018		/* invalidate the icache */ TEXT icacheinvalidate(SB), $-4 MCR CpMMU, 0, R0, C(CpCacheFlush), C(0x9) RET
2000/0901		/* drain write buffer */
2000/0929		TEXT wbflush(SB), $-4
2000/1018		_wbflush:
2000/1007		MCR CpMMU, 0, R0, C(CpCacheFlush), C(0xa), 4
2000/0831		RET
2000/1015/sys/src/9/bitsy/l.s:100,106 – 2000/1018/sys/src/9/bitsy/l.s:144,150
2000/0929		*/ TEXT mmuenable(SB), $-4 MRC CpMMU, 0, R0, C(CpControl), C(0x0)
2000/1015		ORR $(CpCmmuena|CpCwb|CpCdcache), R0
2000/1018		ORR $(CpCmmuena|CpCdcache|CpCwb), R0
2000/0929		MCR CpMMU, 0, R0, C(CpControl), C(0x0) RET