2001/0815/bitsy/l.s (diff list | history)

2001/0814/sys/src/9/bitsy/l.s:563,577 – 2001/0815/sys/src/9/bitsy/l.s:563,568 (short | long | prev | next)
2001/0618		/* SVC mode, interrupts disabled */ MOVW $(PsrDirq|PsrDfiq|PsrMsvc), R1 MOVW R1, CPSR /* flush caches */
2001/0621		MCR CpMMU, 0, R0, C(CpCacheFlush), C(0x7), 0
2001/0618		/* drain prefetch */ MOVW R0,R0 MOVW R0,R0 MOVW R0,R0 MOVW R0,R0 /* drain write buffer */ MCR CpMMU, 0, R0, C(CpCacheFlush), C(0xa), 4 /* gotopowerlabel() */ /* svc */
2001/0811
2001/0814/sys/src/9/bitsy/l.s:581,596 – 2001/0815/sys/src/9/bitsy/l.s:572,591
2001/0809		MOVW R1, SPSR MOVW R2, CPSR
2001/0618		/* copro */
2001/0621		MOVW 148(R0), R3
2001/0618		MCR CpMMU, 0, R3, C(CpTTB), C(0x0)
2001/0815		/* flush caches */ MCR CpMMU, 0, R0, C(CpCacheFlush), C(0x7), 0 /* drain prefetch */ MOVW R0,R0 MOVW R0,R0 MOVW R0,R0 MOVW R0,R0 /* drain write buffer */ MCR CpMMU, 0, R0, C(CpCacheFlush), C(0xa), 4 MCR CpMMU, 0, R0, C(CpTLBFlush), C(0x7)
2001/0621		MOVW 144(R0), R3
2001/0618		MCR CpMMU, 0, R3, C(CpDAC), C(0x0)
2001/0621		MOVW 152(R0), R3
2001/0814		MCR CpMMU, 0, R3, C(CpControl), C(0x0) /* Enable cache */ MOVW R0, R0 MOVW R0, R0 MOVW R0, R0 MOVW R0, R0
2001/0815		MOVW 148(R0), R3 MCR CpMMU, 0, R3, C(CpTTB), C(0x0)
2001/0621		MOVW 156(R0), R3
2001/0618		MCR CpMMU, 0, R3, C(CpFSR), C(0x0)
2001/0621		MOVW 160(R0), R3
2001/0814/sys/src/9/bitsy/l.s:597,603 – 2001/0815/sys/src/9/bitsy/l.s:592,616
2001/0618		MCR CpMMU, 0, R3, C(CpFAR), C(0x0)
2001/0621		MOVW 164(R0), R3
2001/0618		MCR CpMMU, 0, R3, C(CpPID), C(0x0) MCR CpMMU, 0, R0, C(CpTLBFlush), C(0x7)
2001/0815		MOVW 152(R0), R3 MCR CpMMU, 0, R3, C(CpControl), C(0x0) /* Enable cache */ MOVW R0,R0 MOVW R0,R0 MOVW R0,R0 MOVW R0,R0 /* flush i&d caches */ MCR CpMMU, 0, R0, C(CpCacheFlush), C(0x7), 0 /* drain prefetch */ MOVW R0,R0 MOVW R0,R0 MOVW R0,R0 MOVW R0,R0 /* flush tlb */ MCR CpMMU, 0, R0, C(CpTLBFlush), C(0x7), 0 MOVW R0,R0 MOVW R0,R0 MOVW R0,R0 MOVW R0,R0
2001/0618		/* irq */
2001/0621		BIC $(PsrMask), R2, R3 ORR $(PsrDirq|PsrMirq), R3