2001/0818/bitsy/l.s (diff list | history)

2001/0817/sys/src/9/bitsy/l.s:670,702 – 2001/0818/sys/src/9/bitsy/l.s:670,706 (short | long | prev | next)
2001/0618		loop:
2001/0621		B loop
2001/0618
2001/0817		TEXT sa1100_power_down(SB), $-4
2001/0818		TEXT power_down(SB), $-4
2001/0817		/* disable clock switching */ MCR CpPWR, 0, R0, C(CpTest), C(0x2), 2 /* save address of sleep_param in r4 */ mov r0, r4                  @ Adjust memory timing before lowering CPU clock /* Clock speed ajdustment without changing memory timing makes */ /* CPU hang in some cases */ ldr r0, =MDREFR ldr r1, [r0] orr r1, r1, #MDREFR_K1DB2 str r1, [r0]
2001/0818		/* Adjust memory timing before lowering CPU clock * Clock speed ajdustment without changing memory * timing makes CPU hang in some cases */ MOVW $(MEMCONFREGS+0x1c),R0 MOVW (R0),R1 /* mdrefr */ ORR $(1<<22), R1 /* set K1DB2 */ MOVW R1,(R0)
2001/0817		/* delay 90us and set CPU PLL to lowest speed */ /* fixes resume problem on high speed SA1110 */ mov r0, #90 bl SYMBOL_NAME(udelay) ldr r0, =PPCR mov r1, #0 str r1, [r0] mov r0, #90 bl SYMBOL_NAME(udelay)
2001/0818		MOVW $(90*206),R0 d1: SUB $1,R0 BNE d1
2001/0817
2001/0818		MOVW $(POWERREGS+0x14),R0 MOVW $0,R1 MOVW R1,(R0) /* clear PPCR */
2001/0817
2001/0818		MOVW $(90*206),R0 d2: SUB $1,R0 BNE d2
2001/0817		/* setup up register contents for jump to page containing SA1110 SDRAM controller bug fix suspend code * * r0 points to MSC0 register
2001/0817/sys/src/9/bitsy/l.s:716,777 – 2001/0818/sys/src/9/bitsy/l.s:720,781
2001/0817		* */ ldr r0, =MSC0 ldr r1, =MSC1 ldr r2, =MSC2
2001/0818		MOVW $(MEMCONFREGS+0x10),R0 MOVW $(MEMCONFREGS+0x14),R1 MOVW $(MEMCONFREGS+0x2c),R2
2001/0817		ldr r3, [r0] bic r3, r3, #FMsk(MSC_RT) bic r3, r3, #FMsk(MSC_RT)<<16
2001/0818		MOVW (R0),R3 BIC $0x00030003,R3 /* MSC_RT fields */
2001/0817		ldr r4, [r1] bic r4, r4, #FMsk(MSC_RT) bic r4, r4, #FMsk(MSC_RT)<<16
2001/0818		MOVW (R1),R4 BIC $0x00030003,R4 /* MSC_RT fields */
2001/0817		ldr r5, [r2] bic r5, r5, #FMsk(MSC_RT) bic r5, r5, #FMsk(MSC_RT)<<16
2001/0818		MOVW (R2),R5 BIC $0x00030003,R5 /* MSC_RT fields */
2001/0817		ldr r6, =MDREFR
2001/0818		MOVW $(MEMCONFREGS+0x1c),R6
2001/0817		ldr r7, [r6] bic r7, r7, #0x0000FF00 bic r7, r7, #0x000000F0 orr r8, r7, #MDREFR_SLFRSH
2001/0818		MOVW (R6),R7 BIC $0x0000FFF0,R7 /* DRI 0 .. 11 */ ORR $(1<<31),R7,R8 /* prepare to set self refresh */
2001/0817		ldr r9, =MDCNFG ldr r10, [r9] bic r10, r10, #(MDCNFG_DE0+MDCNFG_DE1) bic r10, r10, #(MDCNFG_DE2+MDCNFG_DE3)
2001/0818		MOVW $(MEMCONFREGS+0x0),R9 MOVW (R9),R10 BIC $(0x00030003),R10 /* clear DE0 ⋯ DE3 */
2001/0817		bic r11, r8, #MDREFR_SLFRSH bic r11, r11, #MDREFR_E1PIN
2001/0818		BIC $(1<<31 | 1<<20),R8,R11 /* self-refresh and e1pin */
2001/0817		ldr r12, =PMCR
2001/0818		MOVW $(POWERREGS+0x0),R12 MOVW $1,R13 /* sleep force bit */
2001/0817		mov r13, #PMCR_SF
2001/0818		MOVW R0,R0 MOVW R0,R0 MOVW R0,R0 MOVW R0,R0 MOVW R0,R0 MOVW R0,R0 MOVW R0,R0 /* Fall through */
2001/0817		b sa1110_sdram_controller_fix
2001/0818		/* .align 5 Needs to be on a cache line boundary? */ TEXT sdram_controller_fix(SB),$0
2001/0817		.align 5 sa1110_sdram_controller_fix:                  /* Step 1 clear RT field of all MSCx registers */ str r3, [r0] str r4, [r1] str r5, [r2]
2001/0818		MOVW R3,(R0) MOVW R4,(R1) MOVW R5,(R2)
2001/0817		/* Step 2 clear DRI field in MDREFR */ str r7, [r6]
2001/0818		MOVW R7,(R6)
2001/0817		/* Step 3 set SLFRSH bit in MDREFR */ str r8, [r6]
2001/0818		MOVW R8,(R6)
2001/0817		/* Step 4 clear DE bis in MDCNFG */ str r10, [r9]
2001/0818		MOVW R10,(R9)
2001/0817		/* Step 5 clear DRAM refresh control register */ str r11, [r6]
2001/0818		MOVW R11,(R6)
2001/0817		/* Wow, now the hardware suspend request pins can be used, that makes them functional for */ /* about 7 ns out of the entire time that the CPU is running! */
2001/0817/sys/src/9/bitsy/l.s:778,787 – 2001/0818/sys/src/9/bitsy/l.s:782,791
2001/0817		/* Step 6 set force sleep bit in PMCR */ str r13, [r12]                  20: b 20b /* loop waiting for sleep */
2001/0818		MOVW R13,(R12) slloop: B slloop /* loop waiting for sleep */
2001/0817
2000/1130		/* The first MCR instruction of this function needs to be on a cache-line * boundary; to make this happen, it will be copied (in trap.c).