2001/0821/bitsy/l.s (diff list | history)

2001/0820/sys/src/9/bitsy/l.s:473,483 – 2001/0821/sys/src/9/bitsy/l.s:473,483 (short | long | prev | next)
2000/0831		MOVW $1, R0 RET
2000/1130
2001/0618		/* save the state machine in power_resume[] for an upcoming suspend
2001/0821		/* save the state machine in power_state[] for an upcoming suspend
2001/0618		*/ TEXT setpowerlabel(SB), $-4 MOVW $power_resume+0(SB), R0 /* svc */ /* power_resume[]: what */
2001/0821		MOVW $power_state+0(SB), R0 /* svc */ /* power_state[]: what */
2001/0621		MOVW R1, 0(R0) MOVW R2, 4(R0) MOVW R3, 8(R0)
2001/0820/sys/src/9/bitsy/l.s:558,564 – 2001/0821/sys/src/9/bitsy/l.s:558,564
2001/0618		/* Entered after a resume from suspend state. * The bootldr jumps here after a processor reset.
2001/0620		*/
2001/0618		TEXT sa1100_power_resume(SB), $-4
2001/0821		TEXT power_resume(SB), $-4
2001/0618		MOVW $setR12(SB), R12 /* load the SB */ /* SVC mode, interrupts disabled */ MOVW $(PsrDirq|PsrDfiq|PsrMsvc), R1
2001/0820/sys/src/9/bitsy/l.s:566,572 – 2001/0821/sys/src/9/bitsy/l.s:566,572
2001/0618		/* gotopowerlabel() */ /* svc */
2001/0811
2001/0618		MOVW $power_resume+0(SB), R0
2001/0821		MOVW $power_state+0(SB), R0
2001/0618		MOVW 56(R0), R1 /* R1: SPSR, R2: CPSR */ MOVW 60(R0), R2
2001/0809		MOVW R1, SPSR
2001/0820/sys/src/9/bitsy/l.s:677,685 – 2001/0821/sys/src/9/bitsy/l.s:677,685
2001/0820		MOVW gpioregs+0(SB),R6 MOVW memconfregs+0(SB),R5 MOVW powerregs+0(SB),R3 MOVW 0x1c(R5),R1 ORR $0x30400000,R1 MOVW R1,refr-4(SP)
2001/0821		MOVW 0x1c(R5),R4 ORR $0x30400000,R4 AND $(~0xfff0),R4
2001/0820		MOVW $0x80000003,R2 MOVW R2,0xc(R3) MOVW $15,R2
2001/0820/sys/src/9/bitsy/l.s:688,694 – 2001/0821/sys/src/9/bitsy/l.s:688,694
2001/0820		MOVW R2,0x10(R3) MOVW $0,R2 MOVW R2,0x18(R3) MOVW $sa1100_power_resume+0(SB),R2
2001/0821		MOVW $power_resume+0(SB),R2
2001/0820		MOVW R2,0x8(R3) MOVW $0,R2 MOVW R2,0x4(R6)
2001/0820/sys/src/9/bitsy/l.s:705,747 – 2001/0821/sys/src/9/bitsy/l.s:705,737
2001/0820		l14: SUB $1,R0 BGT l14 MOVW powerregs+0(SB),R5 MOVW refr-4(SP),R4 AND $(~0xfff0),R4 ORR $0x80000000,R4,R6 AND $(~0x80100000),R6,R11
2001/0818
2001/0820		MOVW memconfregs+0(SB),R3 MOVW (R3),R12
2001/0821		MOVW 0x0(R3),R12
2001/0820		AND $(~0x30003),R12
2001/0818
2001/0820		MOVW 0x10(R3),R2 AND $0xfffcfffc,R2
2001/0821		AND $(~0x00030003),R2
2001/0820		MOVW R2,0x10(R3) MOVW 0x14(R3),R2 AND $0xfffcfffc,R2
2001/0821		AND $(~0x00030003),R2
2001/0820		MOVW R2,0x14(R3) MOVW 0x2c(R3),R2 AND $0xfffcfffc,R2
2001/0821		AND $(~0x00030003),R2
2001/0820		MOVW R2,0x2c(R3)
2001/0821		MOVW R0,R0 /* filler */
2001/0817
2001/0820		MOVW $1,R2 MOVW R4,0x1c(R3) // MOVW R6,0x1c(R3) // MOVW R12,(R3)
2001/0821		MOVW R12,0x0(R3)
2001/0820		// MOVW R11,0x1c(R3) MOVW R2,0(R5)
2001/0821		MOVW R2,0x0(R5)
2001/0817
2001/0818		slloop: B slloop /* loop waiting for sleep */
2001/0820		TEXT coma(SB), $-4 MOVW $1,R1 MOVW $(MEMCONFREGS+0x1c),R2 MOVW $(POWERREGS+0x0),R3 // MOVW R0,(R2) MOVW R1,(R3) comaloop: B comaloop
2001/0817
2000/1130		/* The first MCR instruction of this function needs to be on a cache-line * boundary; to make this happen, it will be copied (in trap.c).