plan 9 kernel history: overview | file list | diff list

2003/0326/pc/vganvidia.c (diff list | history)

2002/0502/sys/src/9/pc/vganvidia.c:24,532003/0326/sys/src/9/pc/vganvidia.c:24,30 (short | long | prev | next)
2001/0404    
	hwCurImage = Pramin + (0x00010000 - 0x0800), 
}; 
 
static ushort nvidiadid[] = { 
	0x0020,		/* Riva TNT */ 
	0x0028,		/* Riva TNT2 */ 
	0x0029,		/* Riva TNT2 (Ultra)*/ 
	0x002C,		/* Riva TNT2 (Vanta) */ 
	0x002D,		/* Riva TNT2 M64 */ 
	0x00A0,		/* Riva TNT2 (Integrated) */ 
	0x0100,		/* GeForce 256 */ 
	0x0101,		/* GeForce DDR */ 
	0x0103,		/* Quadro */ 
	0x0110,		/* GeForce2 MX */ 
	0x0111,		/* GeForce2 MX DDR */ 
	0x0112,		/* GeForce 2 Go */ 
	0x0113,		/* Quadro 2 MXR */ 
	0x0150,		/* GeForce2 GTS */ 
	0x0151,		/* GeForce2 GTS (rev 1) */ 
	0x0152,		/* GeForce2 Ultra */ 
	0x0153,		/* Quadro 2 Pro */ 
2002/0409    
	0x0200,		/* GeForce3 */ 
2002/0502    
	0x0201, 
	0x0202, 
2001/0404    
	0, 
}; 
                 
2003/0326    
/* Nvidia is good about backwards compatibility -- any did > 0x20 is fine */ 
2001/0404    
static Pcidev* 
nvidiapci(void) 
{ 
2002/0502/sys/src/9/pc/vganvidia.c:54,702003/0326/sys/src/9/pc/vganvidia.c:31,43
2001/0404    
	Pcidev *p; 
	ushort *did; 
 
	if((p = pcimatch(nil, 0x10DE, 0)) == nil) 
		return nil; 
	for(did = nvidiadid; *did; did++){ 
		if(*did == p->did) 
2003/0326    
	p = nil; 
	while((p = pcimatch(p, 0x10DE, 0)) != nil) 
		if(p->did > 0x20 && p->ccrp == 3)	/* video card */ 
2001/0404    
			return p; 
	} 
                 
	return nil; 
} 
 
                 
static ulong 
nvidialinear(VGAscr* scr, int* size, int* align) 
{ 
2002/0502/sys/src/9/pc/vganvidia.c:82,882003/0326/sys/src/9/pc/vganvidia.c:55,61
2001/0404    
		*size = p->mem[1].size; 
	} 
 
	if(wasupamem) { 
2003/0326    
	if(wasupamem){ 
2001/0404    
		if(oaperture == aperture) 
			return oaperture; 
		upafree(oaperture, oapsize); 
2002/0502/sys/src/9/pc/vganvidia.c:123,1292003/0326/sys/src/9/pc/vganvidia.c:96,102
2001/0404    
		return; 
 
	scr->io = upamalloc(p->mem[0].bar & ~0x0F, p->mem[0].size, 0); 
	if (scr->io == 0) 
2003/0326    
	if(scr->io == 0) 
2001/0404    
		return; 
2001/0908    
	addvgaseg("nvidiammio", scr->io, p->mem[0].size); 
2001/0404    
 
2002/0502/sys/src/9/pc/vganvidia.c:130,1362003/0326/sys/src/9/pc/vganvidia.c:103,109
2001/0404    
	size = p->mem[1].size; 
	align = 0; 
	aperture = nvidialinear(scr, &size, &align); 
	if(aperture) { 
2003/0326    
	if(aperture){ 
2001/0404    
		scr->aperture = aperture; 
		scr->apsize = size; 
2001/0908    
		addvgaseg("nvidiascreen", aperture, size); 
2002/0502/sys/src/9/pc/vganvidia.c:161,1762003/0326/sys/src/9/pc/vganvidia.c:134,149
2001/0404    
 
	p = KADDR(scr->io + hwCurImage); 
 
	for (i=0; i<16; i++) { 
2003/0326    
	for(i=0; i<16; i++) { 
2001/0404    
		c = (curs->clr[2 * i] << 8) | curs->clr[2 * i+1]; 
		s = (curs->set[2 * i] << 8) | curs->set[2 * i+1]; 
		tmp = 0; 
		for (j=0; j<16; j++) { 
2003/0326    
		for (j=0; j<16; j++){ 
2001/0404    
			if(s&0x8000) 
				tmp |= 0x80000000; 
			else if(c&0x8000) 
				tmp |= 0xFFFF0000; 
			if (j&0x1) { 
2003/0326    
			if (j&0x1){ 
2001/0404    
				*p++ = tmp; 
				tmp = 0; 
			} else { 
2002/0502/sys/src/9/pc/vganvidia.c:258,2642003/0326/sys/src/9/pc/vganvidia.c:231,237
2001/0824    
	pgraph = KADDR(scr->io + Pgraph); 
 
	x = 0; 
	while (pgraph[0x00000700/4] & 0x01 && x++ < 1000000) 
2003/0326    
	while(pgraph[0x00000700/4] & 0x01 && x++ < 1000000) 
2001/0824    
		; 
 
	if(x >= 1000000) 
2002/0502/sys/src/9/pc/vganvidia.c:274,2802003/0326/sys/src/9/pc/vganvidia.c:247,253
2001/0824    
	x = 0; 
	fifofree = KADDR(scr->io + Fifo + fifo + 0x10); 
 
	while (((*fifofree >> 2) < entries) && x++ < 1000000) 
2003/0326    
	while(((*fifofree >> 2) < entries) && x++ < 1000000) 
2001/0824    
		; 
 
	if(x >= 1000000) 
2002/0502/sys/src/9/pc/vganvidia.c:328,3342003/0326/sys/src/9/pc/vganvidia.c:301,307
2001/0824    
	seq1 = vgaxi(Seqx, 1) & ~0x20; 
	crtc1A = vgaxi(Crtx, 0x1A) & ~0xC0; 
 
	if(blank) { 
2003/0326    
	if(blank){ 
2001/0824    
		seq1 |= 0x20; 
2001/0901    
//		crtc1A |= 0xC0; 
		crtc1A |= 0x80; 


source code copyright © 1990-2005 Lucent Technologies; see license
Plan 9 distribution
comments to russ cox (rsc@swtch.com)