alphapc/ns16552.h (diff list | history)

1999/0415/sys/src/9/alphapc/ns16552.h:3,8 – 1999/0514/sys/src/9/alphapc/ns16552.h:3,11 (short | long)
1999/0415		#define uartpower(x, y)
1999/0514		void ns16552setup(ulong, ulong, char*, int); void ns16552intr(int);
1999/0415		/* * handle an interrupt to a single uart */
1999/0415/sys/src/9/alphapc/ns16552.h:21,29 – 1999/0514/sys/src/9/alphapc/ns16552.h:24,32
1999/0415		return; already = 1; ns16552setup(Uart0, UartFREQ, "eia0");
1999/0514		ns16552setup(Uart0, UartFREQ, "eia0", Ns550);
1999/0415		intrenable(VectorUART0, ns16552intrx, (void*)0, BUSUNKNOWN); ns16552setup(Uart1, UartFREQ, "eia1");
1999/0514		ns16552setup(Uart1, UartFREQ, "eia1", Ns550);
1999/0415		intrenable(VectorUART1, ns16552intrx, (void*)0, BUSUNKNOWN); }
1999/0514/sys/src/9/alphapc/ns16552.h:5,10 – 2000/0108/sys/src/9/alphapc/ns16552.h:5,11 (short | long)
1999/0415
1999/0514		void ns16552setup(ulong, ulong, char*, int); void ns16552intr(int);
2000/0108		void uartclock(void);
1999/0514
1999/0415		/* * handle an interrupt to a single uart
1999/0514/sys/src/9/alphapc/ns16552.h:28,33 – 2000/0108/sys/src/9/alphapc/ns16552.h:29,35
1999/0415		intrenable(VectorUART0, ns16552intrx, (void*)0, BUSUNKNOWN);
1999/0514		ns16552setup(Uart1, UartFREQ, "eia1", Ns550);
1999/0415		intrenable(VectorUART1, ns16552intrx, (void*)0, BUSUNKNOWN);
2000/0108		addclock0link(uartclock);
1999/0415		} #define RD(r) inb(Uart0+(r))
1999/0514/sys/src/9/alphapc/ns16552.h:43,63 – 2000/0108/sys/src/9/alphapc/ns16552.h:45,47
1999/0415		mb(); } int iprint(char *fmt, ...) { int n, i, s; char buf[512]; va_list arg;                  va_start(arg, fmt); n = doprint(buf, buf+sizeof(buf), fmt, arg) - buf; va_end(arg);                  s = splhi(); for(i = 0; i < n; i++) ns16552iputc(buf[i]); splx(s);                  return n; }
2000/0108/sys/src/9/alphapc/ns16552.h:25,34 – 2000/0401/sys/src/9/alphapc/ns16552.h:25,38 (short | long)
1999/0415		return; already = 1;
2000/0401		if(ioalloc(Uart0, 8, 0, "eia0") < 0) print("eia0: port %d in use\n", Uart0);
1999/0514		ns16552setup(Uart0, UartFREQ, "eia0", Ns550);
1999/0415		intrenable(VectorUART0, ns16552intrx, (void*)0, BUSUNKNOWN);
2000/0401		intrenable(IrqUART0, ns16552intrx, (void*)0, BUSUNKNOWN, "eia0"); if(ioalloc(Uart1, 8, 0, "eia1") < 0) print("eia1: port %d in use\n", Uart1);
1999/0514		ns16552setup(Uart1, UartFREQ, "eia1", Ns550);
1999/0415		intrenable(VectorUART1, ns16552intrx, (void*)0, BUSUNKNOWN);
2000/0401		intrenable(IrqUART1, ns16552intrx, (void*)0, BUSUNKNOWN, "eia1");
2000/0108		addclock0link(uartclock);
1999/0415		}
2000/0401/sys/src/9/alphapc/ns16552.h:1,51 – 2001/0527/sys/src/9/alphapc/ns16552.h:0 (short | long)
Deleted. rsc Mon Mar 7 10:20:28 2005
1999/0415		#define uartwrreg(u,r,v) outb((u)->port + (r), (u)->sticky[r] | (v)) #define uartrdreg(u,r) inb((u)->port + (r))                  #define uartpower(x, y)
1999/0514		void ns16552setup(ulong, ulong, char*, int); void ns16552intr(int);
2000/0108		void uartclock(void);
1999/0514
1999/0415		/* * handle an interrupt to a single uart */ static void ns16552intrx(Ureg*, void* arg) { ns16552intr((ulong)arg); }                  void ns16552install(void) { static int already;                  if(already) return; already = 1;
2000/0401		if(ioalloc(Uart0, 8, 0, "eia0") < 0) print("eia0: port %d in use\n", Uart0);
1999/0514		ns16552setup(Uart0, UartFREQ, "eia0", Ns550);
2000/0401		intrenable(IrqUART0, ns16552intrx, (void*)0, BUSUNKNOWN, "eia0"); if(ioalloc(Uart1, 8, 0, "eia1") < 0) print("eia1: port %d in use\n", Uart1);
1999/0514		ns16552setup(Uart1, UartFREQ, "eia1", Ns550);
2000/0401		intrenable(IrqUART1, ns16552intrx, (void*)0, BUSUNKNOWN, "eia1");
2000/0108		addclock0link(uartclock);
1999/0415		}                  #define RD(r) inb(Uart0+(r)) static void ns16552iputc(char c) { mb(); while((RD(5) & (1<<5)) == 0) mb(); outb(Uart0, c); mb(); while((RD(5) & (1<<5)) == 0) mb(); }