plan 9 kernel history: overview | file list | diff list

1990/1226/ss/io.h (diff list | history)

1990/1223/sys/src/9/ss/io.h:1,6 – 1990/1226/sys/src/9/ss/io.h:1,11 (short | long)
1990/1223    
typedef struct	Duart	Duart; 
 
#define	SYNCREG		((char*)0x40400000) 
#define	DISPLAYRAM	0x02000000
1990/1226    
#define	DISPLAYRAM	0x1E800000 
#define	EPROM		0xF6000000
1990/1223    
#define	DUARTREG	((Duart*)0x40100000) 
#define	PORT		((uchar *)0x40300000)
1990/1226    
 
#define	ENAB		0x40000000	/* ASI 2, System Enable Register */ 
#define	ENABCACHE	0x10 
#define	ENABRESET	0x04
1990/1226/sys/src/9/ss/io.h:3,8 – 1990/1227/sys/src/9/ss/io.h:3,10 (short | long)
1990/1223    
#define	SYNCREG		((char*)0x40400000)
1990/1226    
#define	DISPLAYRAM	0x1E800000 
#define	EPROM		0xF6000000
1990/1227    
#define	CLOCK		0xF3000000 
#define	CLOCKFREQ	1000000		/* one microsecond increments */
1990/1223    
#define	DUARTREG	((Duart*)0x40100000) 
#define	PORT		((uchar *)0x40300000)
1990/1226    
1990/1227/sys/src/9/ss/io.h:1,12 – 1990/1231/sys/src/9/ss/io.h:1,12 (short | long)
1990/1223    
typedef struct	Duart	Duart; 
 
#define	SYNCREG		((char*)0x40400000)
1990/1226    
#define	DISPLAYRAM	0x1E800000 
#define	EPROM		0xF6000000
1990/1227    
#define	CLOCK		0xF3000000 
#define	CLOCKFREQ	1000000		/* one microsecond increments */
1990/1223    
#define	DUARTREG	((Duart*)0x40100000) 
#define	PORT		((uchar *)0x40300000)
1990/1231    
#define	KMDUART		0xF0000000	/* keyboard A, mouse B */ 
#define	ETHER		0xF8C00000	/* RDP, RAP */ 
#define	EEPROM		0xF2000000
1990/1226    
 
#define	ENAB		0x40000000	/* ASI 2, System Enable Register */ 
#define	ENABCACHE	0x10
1990/1231/sys/src/9/ss/io.h:7,12 – 1991/0110/sys/src/9/ss/io.h:7,13 (short | long)
1990/1231    
#define	KMDUART		0xF0000000	/* keyboard A, mouse B */ 
#define	ETHER		0xF8C00000	/* RDP, RAP */ 
#define	EEPROM		0xF2000000
1991/0110    
#define	INTRREG		0xF5000000	/* interrupt register, IO space */
1990/1226    
 
#define	ENAB		0x40000000	/* ASI 2, System Enable Register */ 
#define	ENABCACHE	0x10
1991/0110/sys/src/9/ss/io.h:8,14 – 1991/0111/sys/src/9/ss/io.h:8,10 (short | long)
1990/1231    
#define	ETHER		0xF8C00000	/* RDP, RAP */ 
#define	EEPROM		0xF2000000
1991/0110    
#define	INTRREG		0xF5000000	/* interrupt register, IO space */
1990/1226    
                 
#define	ENAB		0x40000000	/* ASI 2, System Enable Register */ 
#define	ENABCACHE	0x10 
#define	ENABRESET	0x04
1991/0111/sys/src/9/ss/io.h:1,5 – 1991/0604/sys/src/9/ss/io.h:1,3 (short | long)
1990/1223    
typedef struct	Duart	Duart; 
                 
1990/1226    
#define	DISPLAYRAM	0x1E800000 
#define	EPROM		0xF6000000
1990/1227    
#define	CLOCK		0xF3000000
1991/0111/sys/src/9/ss/io.h:8,10 – 1991/0604/sys/src/9/ss/io.h:6,26
1990/1231    
#define	ETHER		0xF8C00000	/* RDP, RAP */ 
#define	EEPROM		0xF2000000
1991/0110    
#define	INTRREG		0xF5000000	/* interrupt register, IO space */
1991/0604    
 
typedef struct SCCdev	SCCdev; 
struct SCCdev 
{ 
	uchar	ptrb; 
	uchar	dummy1; 
	uchar	datab; 
	uchar	dummy2; 
	uchar	ptra; 
	uchar	dummy3; 
	uchar	dataa; 
	uchar	dummy4; 
}; 
 
/* 
 *  crystal frequency for SCC 
 */ 
#define SCCFREQ	10000000
1991/0604/sys/src/9/ss/io.h:2,8 – 1991/1224/sys/src/9/ss/io.h:2,9 (short | long)
1990/1226    
#define	EPROM		0xF6000000
1990/1227    
#define	CLOCK		0xF3000000 
#define	CLOCKFREQ	1000000		/* one microsecond increments */
1990/1231    
#define	KMDUART		0xF0000000	/* keyboard A, mouse B */
1991/1224    
#define	KMDUART0	0xF0000000	/* keyboard A, mouse B */ 
#define	KMDUART1	0xF1000000	/* serial ports */
1990/1231    
#define	ETHER		0xF8C00000	/* RDP, RAP */ 
#define	EEPROM		0xF2000000
1991/0110    
#define	INTRREG		0xF5000000	/* interrupt register, IO space */
1991/1224/sys/src/9/ss/io.h:2,9 – 1991/1225/sys/src/9/ss/io.h:2,9 (short | long)
1990/1226    
#define	EPROM		0xF6000000
1990/1227    
#define	CLOCK		0xF3000000 
#define	CLOCKFREQ	1000000		/* one microsecond increments */
1991/1224    
#define	KMDUART0	0xF0000000	/* keyboard A, mouse B */ 
#define	KMDUART1	0xF1000000	/* serial ports */
1991/1225    
#define	KMDUART		0xF0000000	/* keyboard A, mouse B */ 
#define	EIADUART	0xF1000000	/* serial ports */
1990/1231    
#define	ETHER		0xF8C00000	/* RDP, RAP */ 
#define	EEPROM		0xF2000000
1991/0110    
#define	INTRREG		0xF5000000	/* interrupt register, IO space */
1991/1224/sys/src/9/ss/io.h:21,27 – 1991/1225/sys/src/9/ss/io.h:21,25
1991/0604    
	uchar	dummy4; 
}; 
 
/* 
 *  crystal frequency for SCC 
 */ 
#define SCCFREQ	10000000
1991/1225    
#define KMFREQ	10000000	/* crystal frequency for kbd/mouse 8530 */ 
#define EIAFREQ	5000000		/* crystal frequency for serial port 8530 */
1991/1225/sys/src/9/ss/io.h:4,9 – 1992/0807/sys/src/9/ss/io.h:4,12 (short | long)
Created.
rsc Fri Mar 4 12:44:25 2005
1990/1227    
#define	CLOCKFREQ	1000000		/* one microsecond increments */
1991/1225    
#define	KMDUART		0xF0000000	/* keyboard A, mouse B */ 
#define	EIADUART	0xF1000000	/* serial ports */
1992/0807    
#define	NVRAM		0xF2000000	/* non-volatile RAM */ 
#define DMA		0xF8400000	/* DMA registers */ 
#define SCSI		0xF8800000	/* NCR53C90 registers */
1990/1231    
#define	ETHER		0xF8C00000	/* RDP, RAP */ 
#define	EEPROM		0xF2000000
1991/0110    
#define	INTRREG		0xF5000000	/* interrupt register, IO space */
1991/1225/sys/src/9/ss/io.h:23,25 – 1992/0807/sys/src/9/ss/io.h:26,131
1991/0604    
1991/1225    
#define KMFREQ	10000000	/* crystal frequency for kbd/mouse 8530 */ 
#define EIAFREQ	5000000		/* crystal frequency for serial port 8530 */
1992/0807    
 
/* 
 *  non-volatile ram 
 */ 
#define NVREAD	(2048-8)	/* minus RTC */ 
#define NVWRITE	(2048-8-32)	/* minus RTC, minus ID prom */ 
 
/* 
 * real-time clock (every 4th location) 
 */ 
typedef struct RTCdev	RTCdev; 
struct RTCdev 
{ 
	uchar	control;		/* read or write the device */ 
	uchar	sec; 
	uchar	min; 
	uchar	hour; 
	uchar	wday; 
	uchar	mday; 
	uchar	mon; 
	uchar	year; 
}; 
#define RTCOFF		0x7F8 
#define RTCREAD		(0x40) 
#define RTCWRITE	(0x80) 
 
/* 
 * dma 
 */ 
typedef struct DMAdev DMAdev; 
struct DMAdev { 
	ulong	csr;			/* Control/Status */ 
	ulong	addr;			/* address in 16Mb segment */ 
	ulong	count;			/* transfer byte count */ 
	ulong	diag; 
}; 
 
enum { 
	Int_pend	= 0x00000001,	/* interrupt pending */ 
	Err_pend	= 0x00000002,	/* error pending */ 
	Pack_cnt	= 0x0000000C,	/* pack count (mask) */ 
	Int_en		= 0x00000010,	/* interrupt enable */ 
	Dma_Flush	= 0x00000020,	/* flush pack end error */ 
	Drain		= 0x00000040,	/* drain pack to memory */ 
	Dma_Reset	= 0x00000080,	/* hardware reset (sticky) */ 
	Write		= 0x00000100,	/* set for device to memory (!) */ 
	En_dma		= 0x00000200,	/* enable DMA */ 
	Req_pend	= 0x00000400,	/* request pending */ 
	Byte_addr	= 0x00001800,	/* next byte addr (mask) */ 
	En_cnt		= 0x00002000,	/* enable count */ 
	Tc		= 0x00004000,	/* terminal count */ 
	Ilacc		= 0x00008000,	/* which ether chip */ 
	Dev_id		= 0xF0000000,	/* device ID */ 
}; 
 
/* 
 *  NCR53C90 SCSI controller (every 4th location) 
 */ 
typedef struct SCSIdev	SCSIdev; 
struct SCSIdev { 
	uchar	countlo;		/* byte count, low bits */ 
	uchar	pad1[3]; 
	uchar	counthi;		/* byte count, hi bits */ 
	uchar	pad2[3]; 
	uchar	fifo;			/* data fifo */ 
	uchar	pad3[3]; 
	uchar	cmd;			/* command byte */ 
	uchar	pad4[3]; 
	union { 
		struct {		/* read only... */ 
			uchar	status;		/* status */ 
			uchar	pad05[3]; 
			uchar	intr;		/* interrupt status */ 
			uchar	pad06[3]; 
			uchar	step;		/* sequence step */ 
			uchar	pad07[3]; 
			uchar	fflags;		/* fifo flags */ 
			uchar	pad08[3]; 
			uchar	config;		/* configuration */ 
			uchar	pad09[3]; 
			uchar	Reserved1; 
			uchar	pad0A[3]; 
			uchar	Reserved2; 
			uchar	pad0B[3]; 
		}; 
		struct {		/* write only... */ 
			uchar	destid;		/* destination id */ 
			uchar	pad15[3]; 
			uchar	timeout;	/* during selection */ 
			uchar	pad16[3]; 
			uchar	syncperiod;	/* synchronous xfr period */ 
			uchar	pad17[3]; 
			uchar	syncoffset;	/* synchronous xfr offset */ 
			uchar	pad18[3]; 
			uchar	XXX; 
			uchar	pad19[3]; 
			uchar	clkconf; 
			uchar	pad1A[3]; 
			uchar	test;	 
			uchar	pad1B[3]; 
		}; 
	}; 
};
1992/0807/sys/src/9/ss/io.h:1,4 – 1992/0810/sys/src/9/ss/io.h:1,5 (short | long)
1990/1226    
#define	DISPLAYRAM	0x1E800000
1992/0810    
#define	FRAMEBUFID	0xFE000000 
#define	DISPLAYRAM	0xFE800000
1990/1226    
#define	EPROM		0xF6000000
1990/1227    
#define	CLOCK		0xF3000000 
#define	CLOCKFREQ	1000000		/* one microsecond increments */
1992/0810/sys/src/9/ss/io.h:1,3 – 1992/0813/sys/src/9/ss/io.h:1,4 (short | long)
1992/0813    
#define	FRAMEBUF	0xFE000000
1992/0810    
#define	FRAMEBUFID	0xFE000000 
#define	DISPLAYRAM	0xFE800000
1990/1226    
#define	EPROM		0xF6000000
1992/0810/sys/src/9/ss/io.h:89,95 – 1992/0813/sys/src/9/ss/io.h:90,96
1992/0807    
struct SCSIdev { 
	uchar	countlo;		/* byte count, low bits */ 
	uchar	pad1[3]; 
	uchar	counthi;		/* byte count, hi bits */
1992/0813    
	uchar	countmi;		/* byte count, middle bits */
1992/0807    
	uchar	pad2[3]; 
	uchar	fifo;			/* data fifo */ 
	uchar	pad3[3];
1992/0810/sys/src/9/ss/io.h:105,116 – 1992/0813/sys/src/9/ss/io.h:106,125
1992/0807    
			uchar	pad07[3]; 
			uchar	fflags;		/* fifo flags */ 
			uchar	pad08[3]; 
			uchar	config;		/* configuration */
1992/0813    
			uchar	config;		/* RW: configuration */
1992/0807    
			uchar	pad09[3]; 
			uchar	Reserved1; 
			uchar	pad0A[3]; 
			uchar	Reserved2; 
			uchar	pad0B[3];
1992/0813    
			uchar	conf2;		/* RW: configuration */ 
			uchar	pad0C[3]; 
			uchar	conf3;		/* RW: configuration */ 
			uchar	pad0D[3]; 
			uchar	partid;		/* unique part id */ 
			uchar	pad0E[3]; 
			uchar	fbottom;	/* RW: fifo bottom */ 
			uchar	pad0F[3];
1992/0807    
		}; 
		struct {		/* write only... */ 
			uchar	destid;		/* destination id */
1992/0810/sys/src/9/ss/io.h:121,132 – 1992/0813/sys/src/9/ss/io.h:130,149
1992/0807    
			uchar	pad17[3]; 
			uchar	syncoffset;	/* synchronous xfr offset */ 
			uchar	pad18[3]; 
			uchar	XXX;
1992/0813    
			uchar	RW0;
1992/0807    
			uchar	pad19[3]; 
			uchar	clkconf; 
			uchar	pad1A[3]; 
			uchar	test;	 
			uchar	pad1B[3];
1992/0813    
			uchar	RW1; 
			uchar	pad1C[3]; 
			uchar	RW2; 
			uchar	pad1D[3]; 
			uchar	counthi;	/* byte count, hi bits */ 
			uchar	pad1E[3]; 
			uchar	RW3; 
			uchar	pad1F[3];
1992/0807    
		}; 
	}; 
};
1992/0813/sys/src/9/ss/io.h:1,6 – 1992/0814/sys/src/9/ss/io.h:1,6 (short | long)
1992/0813    
#define	FRAMEBUF	0xFE000000
1992/0810    
#define	FRAMEBUFID	0xFE000000 
#define	DISPLAYRAM	0xFE800000
1992/0814    
#define	FRAMEBUFID	(FRAMEBUF+0x000000) 
#define	DISPLAYRAM	(FRAMEBUF+0x800000)
1990/1226    
#define	EPROM		0xF6000000
1990/1227    
#define	CLOCK		0xF3000000 
#define	CLOCKFREQ	1000000		/* one microsecond increments */
1992/0813/sys/src/9/ss/io.h:36,42 – 1992/0814/sys/src/9/ss/io.h:36,42
1992/0807    
#define NVWRITE	(2048-8-32)	/* minus RTC, minus ID prom */ 
 
/* 
 * real-time clock (every 4th location)
1992/0814    
 * real-time clock
1992/0807    
 */ 
typedef struct RTCdev	RTCdev; 
struct RTCdev
1992/0814/sys/src/9/ss/io.h:1,6 – 1992/0904/sys/src/9/ss/io.h:1,7 (short | long)
1992/0813    
#define	FRAMEBUF	0xFE000000
1992/0814    
#define	FRAMEBUFID	(FRAMEBUF+0x000000) 
#define	DISPLAYRAM	(FRAMEBUF+0x800000)
1992/0904    
#define	SBUS(n)		(0xF8000000+(n)*0x2000000) 
#define	FRAMEBUF(n)	SBUS(n) 
#define	FRAMEBUFID(n)	(SBUS(n)+0x000000) 
#define	DISPLAYRAM(n)	(SBUS(n)+0x800000)
1990/1226    
#define	EPROM		0xF6000000
1990/1227    
#define	CLOCK		0xF3000000 
#define	CLOCKFREQ	1000000		/* one microsecond increments */
1992/0904/sys/src/9/ss/io.h:1,150 – 1993/0501/sys/src/9/ss/io.h:0 (short | long)
Deleted.
rsc Mon Mar 7 10:33:14 2005
1992/0904    
#define	SBUS(n)		(0xF8000000+(n)*0x2000000) 
#define	FRAMEBUF(n)	SBUS(n) 
#define	FRAMEBUFID(n)	(SBUS(n)+0x000000) 
#define	DISPLAYRAM(n)	(SBUS(n)+0x800000)
1990/1226    
#define	EPROM		0xF6000000
1990/1227    
#define	CLOCK		0xF3000000 
#define	CLOCKFREQ	1000000		/* one microsecond increments */
1991/1225    
#define	KMDUART		0xF0000000	/* keyboard A, mouse B */ 
#define	EIADUART	0xF1000000	/* serial ports */
1992/0807    
#define	NVRAM		0xF2000000	/* non-volatile RAM */ 
#define DMA		0xF8400000	/* DMA registers */ 
#define SCSI		0xF8800000	/* NCR53C90 registers */
1990/1231    
#define	ETHER		0xF8C00000	/* RDP, RAP */ 
#define	EEPROM		0xF2000000
1991/0110    
#define	INTRREG		0xF5000000	/* interrupt register, IO space */
1991/0604    
                 
typedef struct SCCdev	SCCdev; 
struct SCCdev 
{ 
	uchar	ptrb; 
	uchar	dummy1; 
	uchar	datab; 
	uchar	dummy2; 
	uchar	ptra; 
	uchar	dummy3; 
	uchar	dataa; 
	uchar	dummy4; 
}; 
                 
1991/1225    
#define KMFREQ	10000000	/* crystal frequency for kbd/mouse 8530 */ 
#define EIAFREQ	5000000		/* crystal frequency for serial port 8530 */
1992/0807    
                 
/* 
 *  non-volatile ram 
 */ 
#define NVREAD	(2048-8)	/* minus RTC */ 
#define NVWRITE	(2048-8-32)	/* minus RTC, minus ID prom */ 
                 
/*
1992/0814    
 * real-time clock
1992/0807    
 */ 
typedef struct RTCdev	RTCdev; 
struct RTCdev 
{ 
	uchar	control;		/* read or write the device */ 
	uchar	sec; 
	uchar	min; 
	uchar	hour; 
	uchar	wday; 
	uchar	mday; 
	uchar	mon; 
	uchar	year; 
}; 
#define RTCOFF		0x7F8 
#define RTCREAD		(0x40) 
#define RTCWRITE	(0x80) 
                 
/* 
 * dma 
 */ 
typedef struct DMAdev DMAdev; 
struct DMAdev { 
	ulong	csr;			/* Control/Status */ 
	ulong	addr;			/* address in 16Mb segment */ 
	ulong	count;			/* transfer byte count */ 
	ulong	diag; 
}; 
                 
enum { 
	Int_pend	= 0x00000001,	/* interrupt pending */ 
	Err_pend	= 0x00000002,	/* error pending */ 
	Pack_cnt	= 0x0000000C,	/* pack count (mask) */ 
	Int_en		= 0x00000010,	/* interrupt enable */ 
	Dma_Flush	= 0x00000020,	/* flush pack end error */ 
	Drain		= 0x00000040,	/* drain pack to memory */ 
	Dma_Reset	= 0x00000080,	/* hardware reset (sticky) */ 
	Write		= 0x00000100,	/* set for device to memory (!) */ 
	En_dma		= 0x00000200,	/* enable DMA */ 
	Req_pend	= 0x00000400,	/* request pending */ 
	Byte_addr	= 0x00001800,	/* next byte addr (mask) */ 
	En_cnt		= 0x00002000,	/* enable count */ 
	Tc		= 0x00004000,	/* terminal count */ 
	Ilacc		= 0x00008000,	/* which ether chip */ 
	Dev_id		= 0xF0000000,	/* device ID */ 
}; 
                 
/* 
 *  NCR53C90 SCSI controller (every 4th location) 
 */ 
typedef struct SCSIdev	SCSIdev; 
struct SCSIdev { 
	uchar	countlo;		/* byte count, low bits */ 
	uchar	pad1[3];
1992/0813    
	uchar	countmi;		/* byte count, middle bits */
1992/0807    
	uchar	pad2[3]; 
	uchar	fifo;			/* data fifo */ 
	uchar	pad3[3]; 
	uchar	cmd;			/* command byte */ 
	uchar	pad4[3]; 
	union { 
		struct {		/* read only... */ 
			uchar	status;		/* status */ 
			uchar	pad05[3]; 
			uchar	intr;		/* interrupt status */ 
			uchar	pad06[3]; 
			uchar	step;		/* sequence step */ 
			uchar	pad07[3]; 
			uchar	fflags;		/* fifo flags */ 
			uchar	pad08[3];
1992/0813    
			uchar	config;		/* RW: configuration */
1992/0807    
			uchar	pad09[3]; 
			uchar	Reserved1; 
			uchar	pad0A[3]; 
			uchar	Reserved2; 
			uchar	pad0B[3];
1992/0813    
			uchar	conf2;		/* RW: configuration */ 
			uchar	pad0C[3]; 
			uchar	conf3;		/* RW: configuration */ 
			uchar	pad0D[3]; 
			uchar	partid;		/* unique part id */ 
			uchar	pad0E[3]; 
			uchar	fbottom;	/* RW: fifo bottom */ 
			uchar	pad0F[3];
1992/0807    
		}; 
		struct {		/* write only... */ 
			uchar	destid;		/* destination id */ 
			uchar	pad15[3]; 
			uchar	timeout;	/* during selection */ 
			uchar	pad16[3]; 
			uchar	syncperiod;	/* synchronous xfr period */ 
			uchar	pad17[3]; 
			uchar	syncoffset;	/* synchronous xfr offset */ 
			uchar	pad18[3];
1992/0813    
			uchar	RW0;
1992/0807    
			uchar	pad19[3]; 
			uchar	clkconf; 
			uchar	pad1A[3]; 
			uchar	test;	 
			uchar	pad1B[3];
1992/0813    
			uchar	RW1; 
			uchar	pad1C[3]; 
			uchar	RW2; 
			uchar	pad1D[3]; 
			uchar	counthi;	/* byte count, hi bits */ 
			uchar	pad1E[3]; 
			uchar	RW3; 
			uchar	pad1F[3];
1992/0807    
		}; 
	}; 
};


source code copyright © 1990-2005 Lucent Technologies; see license
Plan 9 distribution
comments to russ cox (rsc@swtch.com)