plan 9 kernel history: overview | file list | diff list

1995/0517/pc/pci.c (diff list | history)

1995/0517/sys/src/9/pc/pci.c:14,23 – 1995/0721/sys/src/9/pc/pci.c:14,23 (short | long)
1995/0517    
 * nbytes are DWORD aligned. 
 */ 
void 
pcicfgr(uchar busno, uchar devno, uchar funcno, uchar regno, void* data, int nbytes)
1995/0721    
pcicfgr(int busno, int devno, int funcno, int regno, void* data, int nbytes)
1995/0517    
{ 
	ulong base, *p; 
	int len;
1995/0721    
	ulong* p; 
	int base, len;
1995/0517    
 
	lock(&pcicfglock); 
	outb(PCIcse, 0x80|((funcno & 0x07)<<1));
1995/0517/sys/src/9/pc/pci.c:28,34 – 1995/0721/sys/src/9/pc/pci.c:28,34
1995/0517    
	for(len = nbytes/sizeof(ulong); len > 0; len--){ 
		*p = inl(base); 
		p++; 
		base += sizeof(ulong);
1995/0721    
		base += sizeof(*p);
1995/0517    
	} 
 
	outb(PCIcse, 0x00);
1995/0517/sys/src/9/pc/pci.c:35,52 – 1995/0721/sys/src/9/pc/pci.c:35,77
1995/0517    
	unlock(&pcicfglock); 
}
1995/0721    
void 
pcicfgw(int busno, int devno, int funcno, int regno, void* data, int nbytes) 
{ 
	ulong* p; 
	int base, len; 
 
	lock(&pcicfglock); 
	outb(PCIcse, 0x80|((funcno & 0x07)<<1)); 
	outb(PCIforward, busno); 
 
	base = (0xC000|(devno<<8)) + regno; 
	p = data; 
	for(len = nbytes/sizeof(ulong); len > 0; len--){ 
		outl(base, *p); 
		p++; 
		base += sizeof(*p); 
	} 
 
	outb(PCIcse, 0x00); 
	unlock(&pcicfglock); 
}
1995/0517    
int 
pcimatch(uchar busno, uchar devno, PCIcfg* pcicfg)
1995/0721    
pcimatch(int busno, int devno, PCIcfg* pcicfg)
1995/0517    
{ 
	ulong l; 
 
	l = 0; 
	pcicfgr(busno, devno, 0, 0, &l, sizeof(ulong)); 
	if((l & 0xFFFF) != pcicfg->vid) 
		return 0; 
	if(pcicfg->did && ((l>>16) & 0xFFFF) != pcicfg->did) 
		return 0; 
	pcicfgr(busno, devno, 0, 0, pcicfg, sizeof(PCIcfg)); 
                 
	return 1;
1995/0721    
	while(devno < MaxPCI){ 
		l = 0; 
		pcicfgr(busno, devno, 0, 0, &l, sizeof(ulong)); 
		devno++; 
		if((l & 0xFFFF) != pcicfg->vid) 
			continue; 
		if(pcicfg->did && ((l>>16) & 0xFFFF) != pcicfg->did) 
			continue; 
		pcicfgr(busno, devno-1, 0, 0, pcicfg, sizeof(PCIcfg)); 
		return devno; 
	} 
	return -1;
1995/0517    
}
1995/0721/sys/src/9/pc/pci.c:1,3 – 1995/0725/sys/src/9/pc/pci.c:1,7 (short | long)
1995/0725    
/* 
 * Trivial PCI configuration code. 
 * Only deals with bus 0, amongst other glaring omissions. 
 */
1995/0517    
#include "u.h" 
#include "../port/lib.h" 
#include "mem.h"
1995/0721/sys/src/9/pc/pci.c:8,13 – 1995/0725/sys/src/9/pc/pci.c:12,45
1995/0517    
 
static Lock pcicfglock;
1995/0725    
static int pcicfgmode = -1; 
 
static void 
pcicfginit(int) 
{ 
	/* 
	 * Try to determine which PCI configuration mode is implemented. 
	 * Mode2 uses a byte at 0xCF8 and another at 0xCFA; Mode1 uses 
	 * a DWORD at 0xCF8 and another at 0xCFC and will pass through 
	 * any non-DWORD accesses as normal I/O cycles. There shouldn't be 
	 * a device behind theses addresses so if Mode2 accesses fail try 
	 * for Mode1 (which is preferred, Mode2 is deprecated). 
	 */ 
	outb(PCIcse, 0); 
	if(inb(PCIcse) == 0){ 
		pcicfgmode = 2; 
		return; 
	} 
 
	outl(PCIaddr, 0); 
	if(inl(PCIaddr) == 0){ 
		pcicfgmode = 1; 
		return; 
	} 
 
	pcicfgmode = -1; 
}
1995/0517    
/* 
 * Read a chunk of PCI configuration space. 
 * Assumes arguments are within limits and regno and
1995/0721/sys/src/9/pc/pci.c:16,37 – 1995/0725/sys/src/9/pc/pci.c:48,91
1995/0517    
void
1995/0721    
pcicfgr(int busno, int devno, int funcno, int regno, void* data, int nbytes)
1995/0517    
{
1995/0721    
	ulong* p;
1995/0725    
	ulong addr, *p;
1995/0721    
	int base, len;
1995/0517    
 
	lock(&pcicfglock); 
	outb(PCIcse, 0x80|((funcno & 0x07)<<1)); 
	outb(PCIforward, busno);
1995/0725    
	if(pcicfgmode == -1) 
		pcicfginit(busno);
1995/0517    
 
	base = (0xC000|(devno<<8)) + regno; 
	p = data; 
	for(len = nbytes/sizeof(ulong); len > 0; len--){ 
		*p = inl(base); 
		p++;
1995/0721    
		base += sizeof(*p);
1995/0725    
	switch(pcicfgmode){ 
 
	case 1: 
		addr = 0x80000000|((busno & 0xFF)<<16)|((devno & 0x1F)<<11)|((funcno & 0x03)<<8); 
		p = data; 
		for(len = nbytes/sizeof(ulong); len > 0; len--){ 
			outl(PCIaddr, addr|(regno & 0xFF)); 
			*p = inl(PCIdata); 
			p++; 
			regno += sizeof(ulong); 
		} 
	 
		outl(PCIaddr, 0); 
		break; 
 
	case 2: 
		outb(PCIcse, 0x80|((funcno & 0x07)<<1)); 
		outb(PCIforward, busno); 
	 
		base = (0xC000|(devno<<8)) + regno; 
		p = data; 
		for(len = nbytes/sizeof(ulong); len > 0; len--){ 
			*p = inl(base); 
			p++; 
			base += sizeof(*p); 
		} 
	 
		outb(PCIcse, 0); 
		break;
1995/0517    
	} 
 
	outb(PCIcse, 0x00); 
	unlock(&pcicfglock); 
}
1995/0721/sys/src/9/pc/pci.c:38,59 – 1995/0725/sys/src/9/pc/pci.c:92,134
1995/0721    
void 
pcicfgw(int busno, int devno, int funcno, int regno, void* data, int nbytes) 
{ 
	ulong* p;
1995/0725    
	ulong addr, *p;
1995/0721    
	int base, len; 
 
	lock(&pcicfglock); 
	outb(PCIcse, 0x80|((funcno & 0x07)<<1)); 
	outb(PCIforward, busno);
1995/0725    
	if(pcicfgmode == -1) 
		pcicfginit(busno);
1995/0721    
 
	base = (0xC000|(devno<<8)) + regno; 
	p = data; 
	for(len = nbytes/sizeof(ulong); len > 0; len--){ 
		outl(base, *p); 
		p++; 
		base += sizeof(*p);
1995/0725    
	switch(pcicfgmode){ 
 
	case 1: 
		addr = 0x80000000|((busno & 0xFF)<<16)|((devno & 0x1F)<<11)|((funcno & 0x03)<<8); 
		p = data; 
		for(len = nbytes/sizeof(ulong); len > 0; len--){ 
			outl(PCIaddr, addr|(regno & 0xFF)); 
			outl(PCIdata, *p); 
			p++; 
			regno += sizeof(ulong); 
		} 
	 
		outl(PCIaddr, 0); 
		break; 
 
	case 2: 
		outb(PCIcse, 0x80|((funcno & 0x07)<<1)); 
		outb(PCIforward, busno); 
	 
		base = (0xC000|(devno<<8)) + regno; 
		p = data; 
		for(len = nbytes/sizeof(ulong); len > 0; len--){ 
			outl(base, *p); 
			p++; 
			base += sizeof(*p); 
		} 
	 
		outb(PCIcse, 0);
1995/0721    
	} 
 
	outb(PCIcse, 0x00); 
	unlock(&pcicfglock); 
}
1995/0725/sys/src/9/pc/pci.c:71,76 – 1995/0726/sys/src/9/pc/pci.c:71,78 (short | long)
1995/0725    
		break; 
 
	case 2:
1995/0726    
		if(devno >= 16) 
			break;
1995/0725    
		outb(PCIcse, 0x80|((funcno & 0x07)<<1)); 
		outb(PCIforward, busno);
1995/0725/sys/src/9/pc/pci.c:115,120 – 1995/0726/sys/src/9/pc/pci.c:117,124
1995/0725    
		break; 
 
	case 2:
1995/0726    
		if(devno >= 16) 
			break;
1995/0725    
		outb(PCIcse, 0x80|((funcno & 0x07)<<1)); 
		outb(PCIforward, busno);
1995/0725/sys/src/9/pc/pci.c:137,143 – 1995/0726/sys/src/9/pc/pci.c:141,154
1995/0517    
{ 
	ulong l;
1995/0726    
	lock(&pcicfglock); 
	if(pcicfgmode == -1) 
		pcicfginit(busno); 
	unlock(&pcicfglock);
1995/0721    
	while(devno < MaxPCI){
1995/0726    
		if(pcicfgmode == 2 && devno >= 16) 
			break;
1995/0721    
		l = 0; 
		pcicfgr(busno, devno, 0, 0, &l, sizeof(ulong)); 
		devno++;
1995/0726/sys/src/9/pc/pci.c:106,116 – 1995/1206/sys/src/9/pc/pci.c:106,116 (short | long)
1995/0725    
	case 1: 
		addr = 0x80000000|((busno & 0xFF)<<16)|((devno & 0x1F)<<11)|((funcno & 0x03)<<8); 
		p = data; 
		for(len = nbytes/sizeof(ulong); len > 0; len--){
1995/1206    
		for(len = nbytes/sizeof(*p); len > 0; len--){
1995/0725    
			outl(PCIaddr, addr|(regno & 0xFF)); 
			outl(PCIdata, *p); 
			p++; 
			regno += sizeof(ulong);
1995/1206    
			regno += sizeof(*p);
1995/0725    
		} 
	 
		outl(PCIaddr, 0);
1995/0726/sys/src/9/pc/pci.c:124,131 – 1995/1206/sys/src/9/pc/pci.c:124,170
1995/0725    
	 
		base = (0xC000|(devno<<8)) + regno; 
		p = data; 
		for(len = nbytes/sizeof(ulong); len > 0; len--){
1995/1206    
		for(len = nbytes/sizeof(*p); len > 0; len--){
1995/0725    
			outl(base, *p);
1995/1206    
			p++; 
			base += sizeof(*p); 
		} 
	 
		outb(PCIcse, 0); 
	} 
 
	unlock(&pcicfglock); 
} 
 
/* 
 * This is not in the spec, but at least the CMD640B requires it. 
 */ 
void 
pcicfgw8(int busno, int devno, int funcno, int regno, void* data, int nbytes) 
{ 
	uchar *p; 
	int base, len; 
 
	lock(&pcicfglock); 
	if(pcicfgmode == -1) 
		pcicfginit(busno); 
 
	switch(pcicfgmode){ 
 
	default: 
		panic("pcicfgw8: pcicfgmode %d\n", pcicfgmode); 
		break; 
 
	case 2: 
		if(devno >= 16) 
			break; 
		outb(PCIcse, 0x80|((funcno & 0x07)<<1)); 
		outb(PCIforward, busno); 
	 
		base = (0xC000|(devno<<8)) + regno; 
		p = data; 
		for(len = nbytes/sizeof(*p); len > 0; len--){ 
			outb(base, *p);
1995/0725    
			p++; 
			base += sizeof(*p); 
		}
1995/1206/sys/src/9/pc/pci.c:142,147 – 1996/0112/sys/src/9/pc/pci.c:142,148 (short | long)
1995/1206    
void 
pcicfgw8(int busno, int devno, int funcno, int regno, void* data, int nbytes) 
{
1996/0112    
	ulong addr;
1995/1206    
	uchar *p; 
	int base, len;
1995/1206/sys/src/9/pc/pci.c:152,158 – 1996/0112/sys/src/9/pc/pci.c:153,169
1995/1206    
	switch(pcicfgmode){ 
 
	default: 
		panic("pcicfgw8: pcicfgmode %d\n", pcicfgmode);
1996/0112    
		addr = 0x80000000|((busno & 0xFF)<<16)|((devno & 0x1F)<<11)|((funcno & 0x03)<<8); 
		p = data; 
		for(len = nbytes/sizeof(*p); len > 0; len--){ 
			outl(PCIaddr, addr|(regno & 0xFF)); 
			outb(PCIdata, *p); 
			p++; 
			regno += sizeof(*p); 
		} 
	 
		outl(PCIaddr, 0); 
		break;
1995/1206    
		break; 
 
	case 2:
1996/0112/sys/src/9/pc/pci.c:1,6 – 1997/0327/sys/src/9/pc/pci.c:1,7 (short | long)
1995/0725    
/* 
 * Trivial PCI configuration code. 
 * Only deals with bus 0, amongst other glaring omissions.
1997/0327    
 * PCI support code. 
 * To do: 
 *	initialise bridge mappings if the PCI BIOS didn't.
1995/0725    
 */
1995/0517    
#include "u.h" 
#include "../port/lib.h"
1996/0112/sys/src/9/pc/pci.c:10,213 – 1997/0327/sys/src/9/pc/pci.c:11,422
1995/0517    
#include "io.h" 
#include "../port/error.h" 
 
static Lock pcicfglock;
1997/0327    
enum {					/* configuration mechanism #1 */ 
	PciADDR		= 0xCF8,	/* CONFIG_ADDRESS */ 
	PciDATA		= 0xCFC,	/* CONFIG_DATA */
1995/0517    
1997/0327    
					/* configuration mechanism #2 */ 
	PciCSE		= 0xCF8,	/* configuration space enable */ 
	PciFORWARD	= 0xCFA,	/* which bus */ 
 
	MaxFNO		= 7, 
	MaxUBN		= 255, 
}; 
 
static Lock pcicfglock; 
static Lock pcicfginitlock;
1995/0725    
static int pcicfgmode = -1;
1997/0327    
static int pcimaxdno; 
static Pcidev* pciroot;
1995/0725    
 
static void 
pcicfginit(int)
1997/0327    
static int pcicfgrw8(int, int, int, int); 
static int pcicfgrw16(int, int, int, int); 
static int pcicfgrw32(int, int, int, int); 
 
static int 
pciscan(int bno, Pcidev** list)
1995/0725    
{
1997/0327    
	Pcidev *p, *head, *tail; 
	int dno, fno, l, maxfno, maxubn, sbn, tbdf, ubn; 
 
	maxubn = bno; 
	head = tail = 0; 
	for(dno = 0; dno < pcimaxdno; dno++){ 
		maxfno = 0; 
		for(fno = 0; fno <= maxfno; fno++){ 
			/* 
			 * For this possible device, form the bus+device+function 
			 * triplet needed to address it and try to read the vendor 
			 * and device ID. If successful, allocate a device struct 
			 * and start to fill it in with some useful information from 
			 * the device's configuration space. 
			 */ 
			tbdf = MKBUS(BusPCI, bno, dno, fno); 
			l = pcicfgrw32(tbdf, PciVID, 0, 1); 
			if(l == 0xFFFFFFFF || l == 0) 
				continue; 
			p = malloc(sizeof(*p)); 
			p->tbdf = tbdf; 
			p->vid = l; 
			p->did = l>>16; 
			p->bar[0] = pcicfgrw32(tbdf, PciBAR0, 0, 1); 
			p->bar[1] = pcicfgrw32(tbdf, PciBAR1, 0, 1); 
			p->intl = pcicfgrw8(tbdf, PciINTL, 0, 1); 
 
			/* 
			 * Read the base and sub- class and if the device is 
			 * a bridge put it on a list of buses to be descended 
			 * later. 
			 * If it's not a bridge just add it to the tail of the 
			 * device list. 
			 */ 
			l = pcicfgrw16(tbdf, PciCCRu, 0, 1); 
			if(l == ((0x06<<8)|0x04)){ 
				if(head) 
					tail->next = p; 
				else 
					head = p; 
				tail = p; 
			} 
			else{ 
				*list = p; 
				list = &p->next; 
			} 
 
			/* 
			 * If the device is a multi-function device adjust the 
			 * loop count so all possible functions are checked. 
			 */ 
			l = pcicfgrw8(tbdf, PciHDT, 0, 1); 
			if(l & 0x80) 
				maxfno = MaxFNO; 
		} 
	}
1995/0725    
	/* 
	 * Try to determine which PCI configuration mode is implemented. 
	 * Mode2 uses a byte at 0xCF8 and another at 0xCFA; Mode1 uses 
	 * a DWORD at 0xCF8 and another at 0xCFC and will pass through 
	 * any non-DWORD accesses as normal I/O cycles. There shouldn't be 
	 * a device behind theses addresses so if Mode2 accesses fail try 
	 * for Mode1 (which is preferred, Mode2 is deprecated).
1997/0327    
	 * If any bridges were found, recursively descend the tree. 
	 * The end result will be a single list of all devices in ascending 
	 * bus number order.
1995/0725    
	 */ 
	outb(PCIcse, 0); 
	if(inb(PCIcse) == 0){ 
		pcicfgmode = 2; 
		return; 
	}
1997/0327    
	for(p = head; p; p = head){ 
		/* 
		 * Take the primary bridge device off the bridge list 
		 * and link to the end of the final device list. 
		 */ 
		head = p->next; 
		p->next = 0; 
		*list = p; 
		list = &p->next;
1995/0725    
 
	outl(PCIaddr, 0); 
	if(inl(PCIaddr) == 0){ 
		pcicfgmode = 1; 
		return;
1997/0327    
		/* 
		 * If the secondary or subordinate bus number is not initialised 
		 * try to do what the PCI BIOS should have done and fill in the 
		 * numbers as the tree is descended. On the way down the subordinate 
		 * bus number is set to the maximum as it's not known how many 
		 * buses are behind this one; the final value is set on the way 
		 * back up. 
		 */ 
		tbdf = p->tbdf; 
		sbn = pcicfgrw8(tbdf, PciSBN, 0, 1); 
		ubn = pcicfgrw8(tbdf, PciUBN, 0, 1); 
		if(sbn == 0 || ubn == 0){ 
			sbn = maxubn+1; 
			/* 
			 * Make sure memory, I/O and master enables are off, 
			 * set the primary, secondary and subordinate bus numbers 
			 * and clear the secondary status before attempting to 
			 * scan the secondary bus. 
			 * 
			 * Initialisation of the bridge should be done here. 
			 */ 
			pcicfgrw32(tbdf, PciPCR, 0xFFFF0000, 0); 
			l = (MaxUBN<<16)|(sbn<<8)|bno; 
			pcicfgrw32(tbdf, PciPBN, l, 0); 
			pcicfgrw16(tbdf, PciSPSR, 0xFFFF, 0); 
			maxubn = pciscan(sbn, list); 
			l = (maxubn<<16)|(sbn<<8)|bno; 
			pcicfgrw32(tbdf, PciPBN, l, 0); 
		} 
		else{ 
			maxubn = ubn; 
			pciscan(sbn, list); 
		}
1995/0725    
	} 
 
	pcicfgmode = -1;
1997/0327    
	return maxubn;
1995/0725    
}
1995/0517    
/* 
 * Read a chunk of PCI configuration space. 
 * Assumes arguments are within limits and regno and 
 * nbytes are DWORD aligned. 
 */ 
void
1995/0721    
pcicfgr(int busno, int devno, int funcno, int regno, void* data, int nbytes)
1997/0327    
static void 
pcicfginit(void)
1995/0517    
{
1995/0725    
	ulong addr, *p;
1995/0721    
	int base, len;
1997/0327    
	lock(&pcicfginitlock); 
	if(pcicfgmode == -1){ 
		/* 
		 * Try to determine which PCI configuration mode is implemented. 
		 * Mode2 uses a byte at 0xCF8 and another at 0xCFA; Mode1 uses 
		 * a DWORD at 0xCF8 and another at 0xCFC and will pass through 
		 * any non-DWORD accesses as normal I/O cycles. There shouldn't be 
		 * a device behind theses addresses so if Mode2 accesses fail try 
		 * for Mode1 (which is preferred, Mode2 is deprecated). 
		 */ 
		outb(PciCSE, 0); 
		if(inb(PciCSE) == 0){ 
			pcicfgmode = 2; 
			pcimaxdno = 31; 
		} 
		else{ 
			outl(PciADDR, 0); 
			if(inl(PciADDR) == 0){ 
				pcicfgmode = 1; 
				pcimaxdno = 15; 
			} 
		} 
	 
		if(pcicfgmode > 0) 
			pciscan(0, &pciroot); 
	} 
	unlock(&pcicfginitlock); 
}
1995/0517    
 
	lock(&pcicfglock);
1997/0327    
static int 
pcicfgrw8(int tbdf, int rno, int data, int read) 
{ 
	int o, type, x;
1995/0725    
	if(pcicfgmode == -1) 
		pcicfginit(busno);
1997/0327    
		pcicfginit();
1995/0517    
1997/0327    
	if(BUSBNO(tbdf)) 
		type = 0x01; 
	else 
		type = 0x00; 
	x = -1; 
	if(BUSDNO(tbdf) >= pcimaxdno) 
		return x; 
 
	lock(&pcicfglock);
1995/0725    
	switch(pcicfgmode){ 
 
	case 1: 
		addr = 0x80000000|((busno & 0xFF)<<16)|((devno & 0x1F)<<11)|((funcno & 0x03)<<8); 
		p = data; 
		for(len = nbytes/sizeof(ulong); len > 0; len--){ 
			outl(PCIaddr, addr|(regno & 0xFF)); 
			*p = inl(PCIdata); 
			p++; 
			regno += sizeof(ulong); 
		} 
	                 
		outl(PCIaddr, 0);
1997/0327    
		o = rno & 0x03; 
		rno &= ~0x03; 
		outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type); 
		if(read) 
			x = inb(PciDATA+o); 
		else 
			outb(PciDATA+o, data); 
		outl(PciADDR, 0);
1995/0725    
		break; 
 
	case 2:
1995/0726    
		if(devno >= 16) 
			break;
1995/0725    
		outb(PCIcse, 0x80|((funcno & 0x07)<<1)); 
		outb(PCIforward, busno); 
	                 
		base = (0xC000|(devno<<8)) + regno; 
		p = data; 
		for(len = nbytes/sizeof(ulong); len > 0; len--){ 
			*p = inl(base); 
			p++; 
			base += sizeof(*p); 
		} 
	                 
		outb(PCIcse, 0);
1997/0327    
		outb(PciCSE, 0x80|(BUSFNO(tbdf)<<1)); 
		outb(PciFORWARD, BUSBNO(tbdf)); 
		if(read) 
			x = inb((0xC000|(BUSDNO(tbdf)<<8)) + rno); 
		else 
			outb((0xC000|(BUSDNO(tbdf)<<8)) + rno, data); 
		outb(PciCSE, 0);
1995/0725    
		break;
1995/0517    
	} 
                 
	unlock(&pcicfglock);
1997/0327    
 
	return x;
1995/0517    
}
1997/0327    
int 
pcicfgr8(Pcidev* pcidev, int rno) 
{ 
	return pcicfgrw8(pcidev->tbdf, rno, 0, 1); 
}
1995/0721    
void 
pcicfgw(int busno, int devno, int funcno, int regno, void* data, int nbytes)
1997/0327    
pcicfgw8(Pcidev* pcidev, int rno, int data)
1995/0721    
{
1995/0725    
	ulong addr, *p;
1995/0721    
	int base, len;
1997/0327    
	pcicfgrw8(pcidev->tbdf, rno, data, 0); 
}
1995/0721    
 
	lock(&pcicfglock);
1997/0327    
static int 
pcicfgrw16(int tbdf, int rno, int data, int read) 
{ 
	int o, type, x;
1995/0725    
	if(pcicfgmode == -1) 
		pcicfginit(busno);
1997/0327    
		pcicfginit();
1995/0721    
1997/0327    
	if(BUSBNO(tbdf)) 
		type = 0x01; 
	else 
		type = 0x00; 
	x = -1; 
	if(BUSDNO(tbdf) >= pcimaxdno) 
		return x; 
 
	lock(&pcicfglock);
1995/0725    
	switch(pcicfgmode){ 
 
	case 1: 
		addr = 0x80000000|((busno & 0xFF)<<16)|((devno & 0x1F)<<11)|((funcno & 0x03)<<8); 
		p = data;
1995/1206    
		for(len = nbytes/sizeof(*p); len > 0; len--){
1995/0725    
			outl(PCIaddr, addr|(regno & 0xFF)); 
			outl(PCIdata, *p); 
			p++;
1995/1206    
			regno += sizeof(*p);
1995/0725    
		} 
	                 
		outl(PCIaddr, 0);
1997/0327    
		o = rno & 0x02; 
		rno &= ~0x03; 
		outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type); 
		if(read) 
			x = ins(PciDATA+o); 
		else 
			outs(PciDATA+o, data); 
		outl(PciADDR, 0);
1995/0725    
		break; 
 
	case 2:
1995/0726    
		if(devno >= 16) 
			break;
1995/0725    
		outb(PCIcse, 0x80|((funcno & 0x07)<<1)); 
		outb(PCIforward, busno); 
	                 
		base = (0xC000|(devno<<8)) + regno; 
		p = data;
1995/1206    
		for(len = nbytes/sizeof(*p); len > 0; len--){
1995/0725    
			outl(base, *p);
1995/1206    
			p++; 
			base += sizeof(*p); 
		} 
	                 
		outb(PCIcse, 0);
1997/0327    
		outb(PciCSE, 0x80|(BUSFNO(tbdf)<<1)); 
		outb(PciFORWARD, BUSBNO(tbdf)); 
		if(read) 
			x = ins((0xC000|(BUSDNO(tbdf)<<8)) + rno); 
		else 
			outs((0xC000|(BUSDNO(tbdf)<<8)) + rno, data); 
		outb(PciCSE, 0); 
		break;
1995/1206    
	} 
                 
	unlock(&pcicfglock);
1997/0327    
 
	return x;
1995/1206    
} 
 
/* 
 * This is not in the spec, but at least the CMD640B requires it. 
 */
1997/0327    
int 
pcicfgr16(Pcidev* pcidev, int rno) 
{ 
	return pcicfgrw16(pcidev->tbdf, rno, 0, 1); 
}
1995/1206    
void 
pcicfgw8(int busno, int devno, int funcno, int regno, void* data, int nbytes)
1997/0327    
pcicfgw16(Pcidev* pcidev, int rno, int data)
1995/1206    
{
1996/0112    
	ulong addr;
1995/1206    
	uchar *p; 
	int base, len;
1997/0327    
	pcicfgrw16(pcidev->tbdf, rno, data, 0); 
}
1995/1206    
 
	lock(&pcicfglock);
1997/0327    
static int 
pcicfgrw32(int tbdf, int rno, int data, int read) 
{ 
	int type, x;
1995/1206    
	if(pcicfgmode == -1) 
		pcicfginit(busno);
1997/0327    
		pcicfginit();
1995/1206    
1997/0327    
	if(BUSBNO(tbdf)) 
		type = 0x01; 
	else 
		type = 0x00; 
	x = -1; 
	if(BUSDNO(tbdf) >= pcimaxdno) 
		return x; 
 
	lock(&pcicfglock);
1995/1206    
	switch(pcicfgmode){ 
 
	default:
1996/0112    
		addr = 0x80000000|((busno & 0xFF)<<16)|((devno & 0x1F)<<11)|((funcno & 0x03)<<8); 
		p = data; 
		for(len = nbytes/sizeof(*p); len > 0; len--){ 
			outl(PCIaddr, addr|(regno & 0xFF)); 
			outb(PCIdata, *p); 
			p++; 
			regno += sizeof(*p); 
		} 
	                 
		outl(PCIaddr, 0);
1997/0327    
	case 1: 
		rno &= ~0x03; 
		outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type); 
		if(read) 
			x = inl(PciDATA); 
		else 
			outl(PciDATA, data); 
		outl(PciADDR, 0);
1996/0112    
		break;
1995/1206    
		break; 
 
	case 2: 
		if(devno >= 16) 
			break; 
		outb(PCIcse, 0x80|((funcno & 0x07)<<1)); 
		outb(PCIforward, busno); 
	                 
		base = (0xC000|(devno<<8)) + regno; 
		p = data; 
		for(len = nbytes/sizeof(*p); len > 0; len--){ 
			outb(base, *p);
1995/0725    
			p++; 
			base += sizeof(*p); 
		} 
	                 
		outb(PCIcse, 0);
1997/0327    
		outb(PciCSE, 0x80|(BUSFNO(tbdf)<<1)); 
		outb(PciFORWARD, BUSBNO(tbdf)); 
		if(read) 
			x = inl((0xC000|(BUSDNO(tbdf)<<8)) + rno); 
		else 
			outl((0xC000|(BUSDNO(tbdf)<<8)) + rno, data); 
		outb(PciCSE, 0); 
		break;
1995/0721    
	} 
                 
	unlock(&pcicfglock);
1997/0327    
 
	return x;
1995/0721    
}
1995/0517    
int
1995/0721    
pcimatch(int busno, int devno, PCIcfg* pcicfg)
1997/0327    
pcicfgr32(Pcidev* pcidev, int rno)
1995/0517    
{ 
	ulong l;
1997/0327    
	return pcicfgrw32(pcidev->tbdf, rno, 0, 1); 
}
1995/0517    
1995/0726    
	lock(&pcicfglock);
1997/0327    
void 
pcicfgw32(Pcidev* pcidev, int rno, int data) 
{ 
	pcicfgrw32(pcidev->tbdf, rno, data, 0); 
} 
 
Pcidev* 
pcimatch(Pcidev* previous, int vid, int did) 
{ 
	Pcidev *p;
1995/0726    
	if(pcicfgmode == -1) 
		pcicfginit(busno); 
	unlock(&pcicfglock);
1997/0327    
		pcicfginit();
1995/0726    
1995/0721    
	while(devno < MaxPCI){
1995/0726    
		if(pcicfgmode == 2 && devno >= 16) 
			break;
1995/0721    
		l = 0; 
		pcicfgr(busno, devno, 0, 0, &l, sizeof(ulong)); 
		devno++; 
		if((l & 0xFFFF) != pcicfg->vid)
1997/0327    
	if(previous == 0) 
		previous = pciroot; 
	else 
		previous = previous->next; 
 
	for(p = previous; p; p = p->next){ 
		if(p->vid != vid)
1995/0721    
			continue; 
		if(pcicfg->did && ((l>>16) & 0xFFFF) != pcicfg->did) 
			continue; 
		pcicfgr(busno, devno-1, 0, 0, pcicfg, sizeof(PCIcfg)); 
		return devno;
1997/0327    
		if(did == 0 || p->did == did) 
			break;
1995/0721    
	} 
	return -1;
1997/0327    
 
	return p; 
} 
 
void 
pcireset(void) 
{ 
	Pcidev *p; 
	int pcr; 
 
	if(pcicfgmode == -1) 
		pcicfginit(); 
 
	for(p = pciroot; p; p = p->next){ 
		pcr = pcicfgr16(p, PciPSR); 
		pcicfgw16(p, PciPSR, pcr & ~0x04); 
	} 
} 
 
/* 
 * Hack for now to get SYMBIOS controller on-line. 
 */ 
void* 
pcimemmap(int tbdf, int rno, ulong *paddr) 
{ 
	long size; 
	ulong p, v; 
 
	if(pcicfgmode == -1) 
		pcicfginit(); 
 
	v = pcicfgrw32(tbdf, rno, 0, 1); 
	if(v & 1){ 
		print("pcimemmap: not a memory base register\n"); 
		return 0; 
	} 
	if(v & 6){ 
		print("pcimemmap: only 32 bit relocs supported\n"); 
		return 0; 
	} 
	v = 0xFFFFFFFF; 
	pcicfgrw32(tbdf, rno, v, 0); 
	v = pcicfgrw32(tbdf, rno, 0, 1); 
	/* clear out bottom bits and negate to find size */ 
	size = -(v & ~0x0F); 
	v = umbmalloc(0, size, size); 
print("rno %uX, size %uX, v %uX\n", rno, size, v); 
	p = PADDR(v); 
	if(paddr) 
		*paddr = p; 
	pcicfgrw32(tbdf, rno, p, 0); 
	return (void*)v;
1995/0517    
}
1997/0327/sys/src/9/pc/pci.c:162,174 – 1997/0329/sys/src/9/pc/pci.c:162,174 (short | long)
1997/0327    
		outb(PciCSE, 0); 
		if(inb(PciCSE) == 0){ 
			pcicfgmode = 2; 
			pcimaxdno = 31;
1997/0329    
			pcimaxdno = 15;
1997/0327    
		} 
		else{ 
			outl(PciADDR, 0); 
			if(inl(PciADDR) == 0){ 
				pcicfgmode = 1; 
				pcimaxdno = 15;
1997/0329    
				pcimaxdno = 31;
1997/0327    
			} 
		}
1997/0329/sys/src/9/pc/pci.c:41,47 – 1997/0412/sys/src/9/pc/pci.c:41,47 (short | long)
1997/0327    
 
	maxubn = bno; 
	head = tail = 0; 
	for(dno = 0; dno < pcimaxdno; dno++){
1997/0412    
	for(dno = 0; dno <= pcimaxdno; dno++){
1997/0327    
		maxfno = 0; 
		for(fno = 0; fno <= maxfno; fno++){ 
			/*
1997/0329/sys/src/9/pc/pci.c:191,197 – 1997/0412/sys/src/9/pc/pci.c:191,197
1997/0327    
	else 
		type = 0x00; 
	x = -1; 
	if(BUSDNO(tbdf) >= pcimaxdno)
1997/0412    
	if(BUSDNO(tbdf) > pcimaxdno)
1997/0327    
		return x; 
 
	lock(&pcicfglock);
1997/0329/sys/src/9/pc/pci.c:248,254 – 1997/0412/sys/src/9/pc/pci.c:248,254
1997/0327    
	else 
		type = 0x00; 
	x = -1; 
	if(BUSDNO(tbdf) >= pcimaxdno)
1997/0412    
	if(BUSDNO(tbdf) > pcimaxdno)
1997/0327    
		return x; 
 
	lock(&pcicfglock);
1997/0329/sys/src/9/pc/pci.c:305,311 – 1997/0412/sys/src/9/pc/pci.c:305,311
1997/0327    
	else 
		type = 0x00; 
	x = -1; 
	if(BUSDNO(tbdf) >= pcimaxdno)
1997/0412    
	if(BUSDNO(tbdf) > pcimaxdno)
1997/0327    
		return x; 
 
	lock(&pcicfglock);
1997/0412/sys/src/9/pc/pci.c:410,419 – 1997/0711/sys/src/9/pc/pci.c:410,421 (short | long)
1997/0327    
	v = 0xFFFFFFFF; 
	pcicfgrw32(tbdf, rno, v, 0); 
	v = pcicfgrw32(tbdf, rno, 0, 1); 
	/* clear out bottom bits and negate to find size */
1997/0711    
	/* 
	 * Clear out bottom bits and negate to find size. 
	 * If none can be found could try for UPA memory here. 
	 */
1997/0327    
	size = -(v & ~0x0F); 
	v = umbmalloc(0, size, size); 
print("rno %uX, size %uX, v %uX\n", rno, size, v); 
	p = PADDR(v); 
	if(paddr) 
		*paddr = p;
1997/0711/sys/src/9/pc/pci.c:361,367 – 1997/0831/sys/src/9/pc/pci.c:361,367 (short | long)
1997/0327    
	else 
		previous = previous->next; 
 
	for(p = previous; p; p = p->next){
1997/0831    
	for(p = previous; p; p = p->next) {
1997/0327    
		if(p->vid != vid)
1995/0721    
			continue;
1997/0327    
		if(did == 0 || p->did == did)
1997/0831/sys/src/9/pc/pci.c:28,33 – 1997/1011/sys/src/9/pc/pci.c:28,34 (short | long)
1995/0725    
static int pcicfgmode = -1;
1997/0327    
static int pcimaxdno; 
static Pcidev* pciroot;
1997/1011    
static Pcidev* pcilist;
1995/0725    
1997/0327    
static int pcicfgrw8(int, int, int, int); 
static int pcicfgrw16(int, int, int, int);
1997/0831/sys/src/9/pc/pci.c:36,46 – 1997/1011/sys/src/9/pc/pci.c:37,49
1997/0327    
static int 
pciscan(int bno, Pcidev** list)
1995/0725    
{
1997/1011    
	ulong v;
1997/0327    
	Pcidev *p, *head, *tail; 
	int dno, fno, l, maxfno, maxubn, sbn, tbdf, ubn;
1997/1011    
	int dno, fno, i, l, maxfno, maxubn, rno, sbn, tbdf, ubn;
1997/0327    
 
	maxubn = bno; 
	head = tail = 0;
1997/1011    
	head = nil; 
	tail = nil;
1997/0412    
	for(dno = 0; dno <= pcimaxdno; dno++){
1997/0327    
		maxfno = 0; 
		for(fno = 0; fno <= maxfno; fno++){
1997/0831/sys/src/9/pc/pci.c:59,88 – 1997/1011/sys/src/9/pc/pci.c:62,91
1997/0327    
			p->tbdf = tbdf; 
			p->vid = l; 
			p->did = l>>16; 
			p->bar[0] = pcicfgrw32(tbdf, PciBAR0, 0, 1); 
			p->bar[1] = pcicfgrw32(tbdf, PciBAR1, 0, 1);
1997/1011    
			p->list = pcilist; 
			pcilist = p;
1997/0327    
			p->intl = pcicfgrw8(tbdf, PciINTL, 0, 1);
1997/1011    
			p->ccru = pcicfgrw16(tbdf, PciCCRu, 0, 1);
1997/0327    
 
			/* 
			 * Read the base and sub- class and if the device is 
			 * a bridge put it on a list of buses to be descended 
			 * later. 
			 * If it's not a bridge just add it to the tail of the 
			 * device list. 
			 */ 
			l = pcicfgrw16(tbdf, PciCCRu, 0, 1); 
			if(l == ((0x06<<8)|0x04)){ 
				if(head) 
					tail->next = p; 
				else 
					head = p; 
				tail = p;
1997/1011    
			rno = PciBAR0 - 4; 
			for(i = 0; i < nelem(p->mem); i++) { 
				rno += 4; 
				p->mem[i].bar = pcicfgrw32(tbdf, rno, 0, 1); 
				if(i > 0 && p->ccru == ((0x06<<8)|0x04)) 
					continue; 
				pcicfgrw32(tbdf, rno, -1, 0); 
				v = pcicfgrw32(tbdf, rno, 0, 1); 
				pcicfgrw32(tbdf, rno, p->mem[i].bar, 0); 
				p->mem[i].size = -(v & ~0xF);
1997/0327    
			} 
			else{ 
				*list = p; 
				list = &p->next; 
			}
1997/1011    
			if(head != nil) 
				tail->link = p; 
			else 
				head = p; 
			tail = p;
1997/0327    
			/* 
			 * If the device is a multi-function device adjust the 
			 * loop count so all possible functions are checked.
1997/0831/sys/src/9/pc/pci.c:93,112 – 1997/1011/sys/src/9/pc/pci.c:96,120
1997/0327    
		} 
	}
1995/0725    
	/*
1997/0327    
	 * If any bridges were found, recursively descend the tree. 
	 * The end result will be a single list of all devices in ascending 
	 * bus number order.
1995/0725    
	 */
1997/0327    
	for(p = head; p; p = head){
1997/1011    
	*list = head; 
	for(p = head; p != nil; p = p->link){
1997/0327    
		/* 
		 * Take the primary bridge device off the bridge list 
		 * and link to the end of the final device list.
1997/1011    
		 * Find bridges and recursively descend the tree. 
		 * Special case the Intel 82454GX Host-to-PCI bridge, 
		 * there can be two of them. 
		 * Otherwise, only descend PCI-to-PCI bridges.
1997/0327    
		 */ 
		head = p->next; 
		p->next = 0; 
		*list = p; 
		list = &p->next;
1997/1011    
		if(p->ccru == ((0x06<<8)|0) && p->vid == 0x8086 && p->did == 0x84C4){ 
			tbdf = p->tbdf; 
			if((sbn = pcicfgrw8(tbdf, 0x4A, 0, 1)) == 0) 
				continue; 
			ubn = pcicfgrw8(tbdf, 0x4B, 0, 1); 
			maxubn = ubn; 
			pciscan(sbn, &p->bridge); 
			continue; 
		} 
		if(p->ccru != ((0x06<<8)|0x04)) 
			continue;
1995/0725    
1997/0327    
		/* 
		 * If the secondary or subordinate bus number is not initialised
1997/0831/sys/src/9/pc/pci.c:133,145 – 1997/1011/sys/src/9/pc/pci.c:141,153
1997/0327    
			l = (MaxUBN<<16)|(sbn<<8)|bno; 
			pcicfgrw32(tbdf, PciPBN, l, 0); 
			pcicfgrw16(tbdf, PciSPSR, 0xFFFF, 0); 
			maxubn = pciscan(sbn, list);
1997/1011    
			maxubn = pciscan(sbn, &p->bridge);
1997/0327    
			l = (maxubn<<16)|(sbn<<8)|bno; 
			pcicfgrw32(tbdf, PciPBN, l, 0); 
		} 
		else{ 
			maxubn = ubn; 
			pciscan(sbn, list);
1997/1011    
			pciscan(sbn, &p->bridge);
1997/0327    
		}
1995/0725    
	}
1997/0831/sys/src/9/pc/pci.c:348,374 – 1997/1011/sys/src/9/pc/pci.c:356,391
1997/0327    
	pcicfgrw32(pcidev->tbdf, rno, data, 0); 
} 
 
Pcidev* 
pcimatch(Pcidev* previous, int vid, int did)
1997/1011    
ulong 
pcibarsize(Pcidev* p, int rno)
1997/0327    
{ 
	Pcidev *p;
1997/1011    
	ulong v, size;
1997/0327    
1997/1011    
	v = pcicfgrw32(p->tbdf, rno, 0, 1); 
	pcicfgrw32(p->tbdf, rno, 0xFFFFFFF0, 0); 
	size = pcicfgrw32(p->tbdf, rno, 0, 1); 
	pcicfgrw32(p->tbdf, rno, v, 0); 
 
	return -(size & ~0x0F); 
} 
 
Pcidev* 
pcimatch(Pcidev* prev, int vid, int did) 
{
1995/0726    
	if(pcicfgmode == -1)
1997/0327    
		pcicfginit();
1995/0726    
1997/0327    
	if(previous == 0) 
		previous = pciroot;
1997/1011    
	if(prev == nil) 
		prev = pcilist;
1997/0327    
	else 
		previous = previous->next;
1997/1011    
		prev = prev->list;
1997/0327    
1997/0831    
	for(p = previous; p; p = p->next) {
1997/0327    
		if(p->vid != vid)
1995/0721    
			continue;
1997/0327    
		if(did == 0 || p->did == did)
1997/1011    
	while(prev != nil) { 
		if(prev->vid == vid && (did == 0 || prev->did == did))
1997/0327    
			break;
1997/1011    
		prev = prev->list;
1995/0721    
	}
1997/0327    
                 
	return p;
1997/1011    
	return prev;
1997/0327    
} 
 
void
1997/0831/sys/src/9/pc/pci.c:380,388 – 1997/1011/sys/src/9/pc/pci.c:397,435
1997/0327    
	if(pcicfgmode == -1) 
		pcicfginit(); 
 
	for(p = pciroot; p; p = p->next){
1997/1011    
	for(p = pcilist; p != nil; p = p->list){
1997/0327    
		pcr = pcicfgr16(p, PciPSR); 
		pcicfgw16(p, PciPSR, pcr & ~0x04);
1997/1011    
	} 
} 
 
void 
pcihinv(Pcidev* p) 
{ 
	int i; 
	Pcidev *t; 
 
	if(p == nil) { 
		p = pciroot; 
		print("bus dev type vid  did  memory\n"); 
	} 
	for(t = p; t != nil; t = t->link) { 
		print("%d  %2d/%d %.4ux %.4ux %.4ux ", 
			BUSBNO(t->tbdf), BUSDNO(t->tbdf), BUSFNO(t->tbdf), 
			t->ccru, t->vid, t->did); 
 
		for(i = 0; i < nelem(p->mem); i++) { 
			if(t->mem[i].size == 0) 
				continue; 
			print("%d:%.8lux %d ", i, 
				t->mem[i].bar, t->mem[i].size); 
		} 
		print("\n"); 
	} 
	while(p != nil) { 
		if(p->bridge != nil) 
			pcihinv(p->bridge); 
		p = p->link;
1997/0327    
	} 
}
1997/1011/sys/src/9/pc/pci.c:29,34 – 1997/1101/sys/src/9/pc/pci.c:29,35 (short | long)
1997/0327    
static int pcimaxdno; 
static Pcidev* pciroot;
1997/1011    
static Pcidev* pcilist;
1997/1101    
static Pcidev* pcitail;
1995/0725    
1997/0327    
static int pcicfgrw8(int, int, int, int); 
static int pcicfgrw16(int, int, int, int);
1997/1011/sys/src/9/pc/pci.c:62,69 – 1997/1101/sys/src/9/pc/pci.c:63,74
1997/0327    
			p->tbdf = tbdf; 
			p->vid = l; 
			p->did = l>>16;
1997/1011    
			p->list = pcilist; 
			pcilist = p;
1997/1101    
 
			if(pcilist != nil) 
				pcitail->list = p; 
			else 
				pcilist = p; 
			pcitail = p;
1997/1011    
1997/0327    
			p->intl = pcicfgrw8(tbdf, PciINTL, 0, 1);
1997/1011    
			p->ccru = pcicfgrw16(tbdf, PciCCRu, 0, 1);
1997/1101/sys/src/9/pc/pci.c:394,414 – 1998/0108/sys/src/9/pc/pci.c:394,399 (short | long)
1997/0327    
} 
 
void 
pcireset(void) 
{ 
	Pcidev *p; 
	int pcr; 
                 
	if(pcicfgmode == -1) 
		pcicfginit(); 
                 
1997/1011    
	for(p = pcilist; p != nil; p = p->list){
1997/0327    
		pcr = pcicfgr16(p, PciPSR); 
		pcicfgw16(p, PciPSR, pcr & ~0x04);
1997/1011    
	} 
} 
                 
void 
pcihinv(Pcidev* p) 
{ 
	int i;
1997/1101/sys/src/9/pc/pci.c:419,427 – 1998/0108/sys/src/9/pc/pci.c:404,412
1997/1011    
		print("bus dev type vid  did  memory\n"); 
	} 
	for(t = p; t != nil; t = t->link) { 
		print("%d  %2d/%d %.4ux %.4ux %.4ux ",
1998/0108    
		print("%d  %2d/%d %.4ux %.4ux %.4ux %d ",
1997/1011    
			BUSBNO(t->tbdf), BUSDNO(t->tbdf), BUSFNO(t->tbdf), 
			t->ccru, t->vid, t->did);
1998/0108    
			t->ccru, t->vid, t->did, t->intl);
1997/1011    
 
		for(i = 0; i < nelem(p->mem); i++) { 
			if(t->mem[i].size == 0)
1997/1101/sys/src/9/pc/pci.c:473,476 – 1998/0108/sys/src/9/pc/pci.c:458,476
1997/0327    
		*paddr = p; 
	pcicfgrw32(tbdf, rno, p, 0); 
	return (void*)v;
1998/0108    
} 
 
void 
pcireset(void) 
{ 
	Pcidev *p; 
	int pcr; 
 
	if(pcicfgmode == -1) 
		pcicfginit(); 
 
	for(p = pcilist; p != nil; p = p->list){ 
		pcr = pcicfgr16(p, PciPSR); 
		pcicfgw16(p, PciPSR, pcr & ~0x04); 
	}
1995/0517    
}
1998/0108/sys/src/9/pc/pci.c:31,38 – 1998/0312/sys/src/9/pc/pci.c:31,36 (short | long)
1997/1011    
static Pcidev* pcilist;
1997/1101    
static Pcidev* pcitail;
1995/0725    
1997/0327    
static int pcicfgrw8(int, int, int, int); 
static int pcicfgrw16(int, int, int, int); 
static int pcicfgrw32(int, int, int, int); 
 
static int
1998/0108/sys/src/9/pc/pci.c:40,46 – 1998/0312/sys/src/9/pc/pci.c:38,44
1995/0725    
{
1997/1011    
	ulong v;
1997/0327    
	Pcidev *p, *head, *tail;
1997/1011    
	int dno, fno, i, l, maxfno, maxubn, rno, sbn, tbdf, ubn;
1998/0312    
	int dno, fno, i, hdt, l, maxfno, maxubn, rno, sbn, tbdf, ubn;
1997/0327    
 
	maxubn = bno;
1997/1011    
	head = nil;
1998/0108/sys/src/9/pc/pci.c:70,88 – 1998/0312/sys/src/9/pc/pci.c:68,118
1997/1101    
				pcilist = p; 
			pcitail = p;
1997/1011    
1997/0327    
			p->intl = pcicfgrw8(tbdf, PciINTL, 0, 1);
1997/1011    
			p->ccru = pcicfgrw16(tbdf, PciCCRu, 0, 1);
1998/0312    
			p->intl = pcicfgr8(p, PciINTL); 
			p->ccru = pcicfgr16(p, PciCCRu);
1997/0327    
1997/1011    
			rno = PciBAR0 - 4; 
			for(i = 0; i < nelem(p->mem); i++) { 
				rno += 4; 
				p->mem[i].bar = pcicfgrw32(tbdf, rno, 0, 1); 
				if(i > 0 && p->ccru == ((0x06<<8)|0x04)) 
					continue; 
				pcicfgrw32(tbdf, rno, -1, 0); 
				v = pcicfgrw32(tbdf, rno, 0, 1); 
				pcicfgrw32(tbdf, rno, p->mem[i].bar, 0); 
				p->mem[i].size = -(v & ~0xF);
1998/0312    
			/* 
			 * If the device is a multi-function device adjust the 
			 * loop count so all possible functions are checked. 
			 */ 
			hdt = pcicfgr8(p, PciHDT); 
			if(hdt & 0x80) 
				maxfno = MaxFNO; 
 
			/* 
			 * If appropriate, read the base address registers 
			 * and work out the sizes. 
			 */ 
			switch(p->ccru>>8){ 
 
			case 0x01:		/* mass storage controller */ 
			case 0x02:		/* network controller */ 
			case 0x03:		/* display controller */ 
			case 0x04:		/* multimedia device */ 
			case 0x07:		/* simple communication controllers */ 
			case 0x08:		/* base system peripherals */ 
			case 0x09:		/* input devices */ 
			case 0x0A:		/* docking stations */ 
			case 0x0B:		/* processors */ 
			case 0x0C:		/* serial bus controllers */ 
				if((hdt & 0x7F) != 0) 
					break; 
				rno = PciBAR0 - 4; 
				for(i = 0; i < nelem(p->mem); i++){ 
					rno += 4; 
					p->mem[i].bar = pcicfgr32(p, rno); 
					pcicfgw32(p, rno, -1); 
					v = pcicfgr32(p, rno); 
					pcicfgw32(p, rno, p->mem[i].bar); 
					p->mem[i].size = -(v & ~0xF); 
				} 
				break; 
 
			case 0x00: 
			case 0x05:		/* memory controller */ 
			case 0x06:		/* bridge device */ 
			default: 
				break;
1997/0327    
			}
1997/1011    
			if(head != nil)
1998/0108/sys/src/9/pc/pci.c:90,103 – 1998/0312/sys/src/9/pc/pci.c:120,125
1997/1011    
			else 
				head = p; 
			tail = p; 
                 
1997/0327    
			/* 
			 * If the device is a multi-function device adjust the 
			 * loop count so all possible functions are checked. 
			 */ 
			l = pcicfgrw8(tbdf, PciHDT, 0, 1); 
			if(l & 0x80) 
				maxfno = MaxFNO; 
		} 
	}
1998/0108/sys/src/9/pc/pci.c:104,123 – 1998/0312/sys/src/9/pc/pci.c:126,133
1997/1011    
	*list = head; 
	for(p = head; p != nil; p = p->link){
1997/0327    
		/*
1997/1011    
		 * Find bridges and recursively descend the tree. 
		 * Special case the Intel 82454GX Host-to-PCI bridge, 
		 * there can be two of them. 
		 * Otherwise, only descend PCI-to-PCI bridges.
1998/0312    
		 * Find PCI-PCI bridges and recursively descend the tree.
1997/0327    
		 */
1997/1011    
		if(p->ccru == ((0x06<<8)|0) && p->vid == 0x8086 && p->did == 0x84C4){ 
			tbdf = p->tbdf; 
			if((sbn = pcicfgrw8(tbdf, 0x4A, 0, 1)) == 0) 
				continue; 
			ubn = pcicfgrw8(tbdf, 0x4B, 0, 1); 
			maxubn = ubn; 
			pciscan(sbn, &p->bridge); 
			continue; 
		} 
		if(p->ccru != ((0x06<<8)|0x04)) 
			continue;
1995/0725    
1998/0108/sys/src/9/pc/pci.c:129,137 – 1998/0312/sys/src/9/pc/pci.c:139,146
1997/0327    
		 * buses are behind this one; the final value is set on the way 
		 * back up. 
		 */ 
		tbdf = p->tbdf; 
		sbn = pcicfgrw8(tbdf, PciSBN, 0, 1); 
		ubn = pcicfgrw8(tbdf, PciUBN, 0, 1);
1998/0312    
		sbn = pcicfgr8(p, PciSBN); 
		ubn = pcicfgr8(p, PciUBN);
1997/0327    
		if(sbn == 0 || ubn == 0){ 
			sbn = maxubn+1; 
			/*
1998/0108/sys/src/9/pc/pci.c:142,154 – 1998/0312/sys/src/9/pc/pci.c:151,163
1997/0327    
			 * 
			 * Initialisation of the bridge should be done here. 
			 */ 
			pcicfgrw32(tbdf, PciPCR, 0xFFFF0000, 0);
1998/0312    
			pcicfgw32(p, PciPCR, 0xFFFF0000);
1997/0327    
			l = (MaxUBN<<16)|(sbn<<8)|bno; 
			pcicfgrw32(tbdf, PciPBN, l, 0); 
			pcicfgrw16(tbdf, PciSPSR, 0xFFFF, 0);
1998/0312    
			pcicfgw32(p, PciPBN, l); 
			pcicfgw16(p, PciSPSR, 0xFFFF);
1997/1011    
			maxubn = pciscan(sbn, &p->bridge);
1997/0327    
			l = (maxubn<<16)|(sbn<<8)|bno; 
			pcicfgrw32(tbdf, PciPBN, l, 0);
1998/0312    
			pcicfgw32(p, PciPBN, l);
1997/0327    
		} 
		else{ 
			maxubn = ubn;
1998/0108/sys/src/9/pc/pci.c:162,167 – 1998/0312/sys/src/9/pc/pci.c:171,180
1997/0327    
static void 
pcicfginit(void)
1995/0517    
{
1998/0312    
	char *p; 
	int bno; 
	Pcidev **list;
1997/0327    
	lock(&pcicfginitlock); 
	if(pcicfgmode == -1){ 
		/*
1998/0108/sys/src/9/pc/pci.c:169,175 – 1998/0312/sys/src/9/pc/pci.c:182,188
1997/0327    
		 * Mode2 uses a byte at 0xCF8 and another at 0xCFA; Mode1 uses 
		 * a DWORD at 0xCF8 and another at 0xCFC and will pass through 
		 * any non-DWORD accesses as normal I/O cycles. There shouldn't be 
		 * a device behind theses addresses so if Mode2 accesses fail try
1998/0312    
		 * a device behind these addresses so if Mode2 accesses fail try
1997/0327    
		 * for Mode1 (which is preferred, Mode2 is deprecated). 
		 */ 
		outb(PciCSE, 0);
1998/0108/sys/src/9/pc/pci.c:185,192 – 1998/0312/sys/src/9/pc/pci.c:198,215
1997/0327    
			} 
		} 
	 
		if(pcicfgmode > 0) 
			pciscan(0, &pciroot);
1998/0312    
		if(pcicfgmode > 0){ 
			if(p = getconf("*pcimaxdno")) 
				pcimaxdno = strtoul(p, 0, 0); 
 
			list = &pciroot; 
			for(bno = 0; bno < 256; bno++){ 
				bno = pciscan(bno, list); 
				while(*list && (*list)->link) 
					list = &(*list)->link; 
			} 
				 
		}
1997/0327    
	} 
	unlock(&pcicfginitlock); 
}
1998/0108/sys/src/9/pc/pci.c:361,379 – 1998/0312/sys/src/9/pc/pci.c:384,389
1997/0327    
	pcicfgrw32(pcidev->tbdf, rno, data, 0); 
}
1997/1011    
ulong 
pcibarsize(Pcidev* p, int rno)
1997/0327    
{
1997/1011    
	ulong v, size;
1997/0327    
                 
1997/1011    
	v = pcicfgrw32(p->tbdf, rno, 0, 1); 
	pcicfgrw32(p->tbdf, rno, 0xFFFFFFF0, 0); 
	size = pcicfgrw32(p->tbdf, rno, 0, 1); 
	pcicfgrw32(p->tbdf, rno, v, 0); 
                 
	return -(size & ~0x0F); 
} 
                 
Pcidev* 
pcimatch(Pcidev* prev, int vid, int did) 
{
1998/0108/sys/src/9/pc/pci.c:421,463 – 1998/0312/sys/src/9/pc/pci.c:431,436
1997/1011    
			pcihinv(p->bridge); 
		p = p->link;
1997/0327    
	} 
} 
                 
/* 
 * Hack for now to get SYMBIOS controller on-line. 
 */ 
void* 
pcimemmap(int tbdf, int rno, ulong *paddr) 
{ 
	long size; 
	ulong p, v; 
                 
	if(pcicfgmode == -1) 
		pcicfginit(); 
                 
	v = pcicfgrw32(tbdf, rno, 0, 1); 
	if(v & 1){ 
		print("pcimemmap: not a memory base register\n"); 
		return 0; 
	} 
	if(v & 6){ 
		print("pcimemmap: only 32 bit relocs supported\n"); 
		return 0; 
	} 
	v = 0xFFFFFFFF; 
	pcicfgrw32(tbdf, rno, v, 0); 
	v = pcicfgrw32(tbdf, rno, 0, 1);
1997/0711    
	/* 
	 * Clear out bottom bits and negate to find size. 
	 * If none can be found could try for UPA memory here. 
	 */
1997/0327    
	size = -(v & ~0x0F); 
	v = umbmalloc(0, size, size); 
	p = PADDR(v); 
	if(paddr) 
		*paddr = p; 
	pcicfgrw32(tbdf, rno, p, 0); 
	return (void*)v;
1998/0108    
} 
 
void
1998/0312/sys/src/9/pc/pci.c:411,420 – 1998/0322/sys/src/9/pc/pci.c:411,420 (short | long)
Fiddle with formatting.
rsc Fri Mar 4 12:44:25 2005
1997/1011    
 
	if(p == nil) { 
		p = pciroot; 
		print("bus dev type vid  did  memory\n");
1998/0322    
		print("bus dev type vid  did intl memory\n");
1997/1011    
	} 
	for(t = p; t != nil; t = t->link) {
1998/0108    
		print("%d  %2d/%d %.4ux %.4ux %.4ux %d ",
1998/0322    
		print("%d  %2d/%d %.4ux %.4ux %.4ux %2d  ",
1997/1011    
			BUSBNO(t->tbdf), BUSDNO(t->tbdf), BUSFNO(t->tbdf),
1998/0108    
			t->ccru, t->vid, t->did, t->intl);
1997/1011    
1998/0322/sys/src/9/pc/pci.c:205,211 – 1998/0324/sys/src/9/pc/pci.c:205,211 (short | long)
Bug fix: walk down to end of list, not just one before.
rsc Fri Mar 4 12:44:25 2005
1998/0312    
			list = &pciroot; 
			for(bno = 0; bno < 256; bno++){ 
				bno = pciscan(bno, list); 
				while(*list && (*list)->link)
1998/0324    
				while(*list)
1998/0312    
					list = &(*list)->link; 
			}
1998/0324/sys/src/9/pc/pci.c:395,406 – 1998/0906/sys/src/9/pc/pci.c:395,421 (short | long)
1997/0327    
	else
1997/1011    
		prev = prev->list;
1997/0327    
1997/1011    
	while(prev != nil) {
1998/0906    
	while(prev != nil){
1997/1011    
		if(prev->vid == vid && (did == 0 || prev->did == did))
1997/0327    
			break;
1997/1011    
		prev = prev->list;
1995/0721    
	}
1997/1011    
	return prev;
1998/0906    
} 
 
Pcidev* 
pcimatchtbdf(int tbdf) 
{ 
	Pcidev *pcidev; 
 
	if(pcicfgmode == -1) 
		pcicfginit(); 
 
	for(pcidev = pcilist; pcidev != nil; pcidev = pcidev->list){ 
		if(pcidev->tbdf == tbdf) 
			break; 
	} 
	return pcidev;
1997/0327    
} 
 
void
1998/0906/sys/src/9/pc/pci.c:396,402 – 1998/1121/sys/src/9/pc/pci.c:396,402 (short | long)
1997/1011    
		prev = prev->list;
1997/0327    
1998/0906    
	while(prev != nil){
1997/1011    
		if(prev->vid == vid && (did == 0 || prev->did == did))
1998/1121    
		if((vid == 0 || prev->vid == vid) && (did == 0 || prev->did == did))
1997/0327    
			break;
1997/1011    
		prev = prev->list;
1995/0721    
	}
1998/1121/sys/src/9/pc/pci.c:1,7 – 1999/0301/sys/src/9/pc/pci.c:1,5 (short | long)
1995/0725    
/*
1997/0327    
 * PCI support code. 
 * To do: 
 *	initialise bridge mappings if the PCI BIOS didn't.
1995/0725    
 */
1995/0517    
#include "u.h" 
#include "../port/lib.h"
1998/1121/sys/src/9/pc/pci.c:11,17 – 1999/0301/sys/src/9/pc/pci.c:9,16
1995/0517    
#include "io.h" 
#include "../port/error.h"
1997/0327    
enum {					/* configuration mechanism #1 */
1999/0301    
enum 
{					/* configuration mechanism #1 */
1997/0327    
	PciADDR		= 0xCF8,	/* CONFIG_ADDRESS */ 
	PciDATA		= 0xCFC,	/* CONFIG_DATA */
1995/0517    
1998/1121/sys/src/9/pc/pci.c:21,28 – 1999/0301/sys/src/9/pc/pci.c:20,41
1997/0327    
 
	MaxFNO		= 7, 
	MaxUBN		= 255,
1999/0301    
 
	BARio		= 0,		/* fake BAR registers for bridges */ 
	BARmem, 
 
	NOBIOS		= 0,		/* initialise if the BIOS didn't */
1997/0327    
};
1999/0301    
enum {					/* command register */ 
	IOen		= (1<<0), 
	MEMen		= (1<<1), 
	MASen		= (1<<2), 
	MemWrInv	= (1<<4), 
	PErrEn		= (1<<6), 
	SErrEn		= (1<<8), 
};
1997/0327    
static Lock pcicfglock; 
static Lock pcicfginitlock;
1995/0725    
static int pcicfgmode = -1;
1998/1121/sys/src/9/pc/pci.c:32,42 – 1999/0301/sys/src/9/pc/pci.c:45,194
1997/1101    
static Pcidev* pcitail;
1995/0725    
1997/0327    
static int pcicfgrw32(int, int, int, int);
1999/0301    
static int pcicfgrw8(int, int, int, int);
1997/0327    
1999/0301    
ulong 
pcibarsize(Pcidev *p, int rno) 
{ 
	ulong v, size; 
 
	v = pcicfgrw32(p->tbdf, rno, 0, 1); 
	pcicfgrw32(p->tbdf, rno, 0xFFFFFFF0, 0); 
	size = pcicfgrw32(p->tbdf, rno, 0, 1); 
	if(v & 1) 
		size |= 0xFFFF0000; 
	pcicfgrw32(p->tbdf, rno, v, 0); 
 
	return -(size & ~0x0F); 
} 
 
static void 
pcibusmap(Pcidev *p, ulong *pmema, ulong *pioa, int wrreg) 
{ 
	int i, size, k; 
	ulong addr, v, mema, ioa, pcr, tmema, tioa; 
 
	if(!NOBIOS) 
		return; 
 
	mema = *pmema; 
	ioa = *pioa; 
 
	print("pcibusmap wr=%d %d.%d.%d mem=%lux io=%lux\n",  
		wrreg, BUSBNO(p->tbdf), BUSDNO(p->tbdf), BUSFNO(p->tbdf), 
		mema, ioa); 
 
	/* 
	 * Allocate address space on this bus 
	 * note this loop follows link, not list 
	 */ 
	for(; p; p = p->link) { 
		if(p->ccrb == 0x06) { 
			if(p->ccru != 0x04) { 
				print("pci: ignored bridge %d.%d.%d\n", 
					BUSBNO(p->tbdf), 
					BUSDNO(p->tbdf), 
					BUSFNO(p->tbdf)); 
				continue; 
			} 
 
			/* Base */ 
			p->mem[BARio].bar = ioa; 
			p->mem[BARmem].bar = mema; 
			tioa = ioa; 
			tmema = mema; 
 
			/* Limit */ 
			ioa += p->mem[BARio].size; 
			mema += p->mem[BARmem].size; 
 
			if(wrreg == 0) 
				continue; 
 
			pcibusmap(p->bridge, &tmema, &tioa, 1); 
 
			/* 
			 * IO base[15:12], IO limit [15:12] 
			 */ 
			v =	(0xFFFF<<16)| 
				(ioa & 0xF000)| 
				((p->mem[BARio].bar & 0xF000)>>8); 
 
			pcicfgrw32(p->tbdf, PciBAR3, v, 0); 
 
			/* 
			 * Memory Base/Limit 
			 */ 
			v =	(mema & ~((1<<20)-1)) | 
				((p->mem[BARmem].bar & ~((1<<20)-1)) >> 16); 
 
			pcicfgrw32(p->tbdf, PciBAR4, v, 0); 
 
			/* 
			 * Disable memory prefetch 
			 */ 
			pcicfgrw32(p->tbdf, PciBAR5, 0x0000FFFF, 0); 
 
			/* 
			 * Enable the bridge 
			 */ 
			v = 0xFFFF0000 | IOen | MEMen | MASen; 
			pcicfgrw32(p->tbdf, PciPCR, v, 0); 
			continue; 
		} 
 
		pcr = pcicfgrw32(p->tbdf, PciPCR, 0, 1); 
		 
		for(i = PciBAR0; i <= PciBAR5; i += 4) { 
			v = pcicfgrw32(p->tbdf, i, 0, 1); 
			size = pcibarsize(p, i); 
			if(size > 16*1024*1024) 
				print("pcimap: size %d?\n", size); 
			if(size == 0) 
				continue; 
 
			if(v & 1) {		/* Allocate IO space */ 
				ioa = (ioa+size-1) & ~(size-1); 
				addr = ioa; 
				ioa += size; 
				pcr |= IOen; 
			} 
			else {			/* Allocate Memory space */ 
				mema = (mema+size-1) & ~(size-1); 
				addr = mema; 
				mema += size; 
				pcr |= MEMen; 
			} 
 
			k = (i-PciBAR0)/4; 
			p->mem[k].size = size; 
			p->mem[k].bar = addr; 
			if(wrreg) 
				pcicfgrw32(p->tbdf, i, addr, 0); 
		} 
 
		/* 
		 * Set latency timer 
		 * Enable memory/io/master 
		 */ 
		if(wrreg) { 
			pcicfgrw8(p->tbdf, PciLTR, 64, 0); 
 
			pcr |= MASen; 
			pcicfgrw32(p->tbdf, PciPCR, pcr, 0); 
		} 
	} 
 
	print("pcibusmap mem=%lux io=%lux\n", mema, ioa); 
 
	*pmema = mema; 
	*pioa = ioa; 
}
1997/0327    
static int 
pciscan(int bno, Pcidev** list)
1995/0725    
{
1997/1011    
	ulong v;
1999/0301    
	ulong mema, ioa;
1997/0327    
	Pcidev *p, *head, *tail;
1998/0312    
	int dno, fno, i, hdt, l, maxfno, maxubn, rno, sbn, tbdf, ubn;
1997/0327    
1998/1121/sys/src/9/pc/pci.c:47,57 – 1999/0301/sys/src/9/pc/pci.c:199,210
1997/0327    
		maxfno = 0; 
		for(fno = 0; fno <= maxfno; fno++){ 
			/* 
			 * For this possible device, form the bus+device+function 
			 * triplet needed to address it and try to read the vendor 
			 * and device ID. If successful, allocate a device struct 
			 * and start to fill it in with some useful information from 
			 * the device's configuration space.
1999/0301    
			 * For this possible device, form the 
			 * bus+device+function triplet needed to address it 
			 * and try to read the vendor and device ID. 
			 * If successful, allocate a device struct and 
			 * start to fill it in with some useful information 
			 * from the device's configuration space.
1997/0327    
			 */ 
			tbdf = MKBUS(BusPCI, bno, dno, fno); 
			l = pcicfgrw32(tbdf, PciVID, 0, 1);
1998/1121/sys/src/9/pc/pci.c:69,75 – 1999/0301/sys/src/9/pc/pci.c:222,230
1997/1101    
			pcitail = p;
1997/1011    
1998/0312    
			p->intl = pcicfgr8(p, PciINTL); 
			p->ccru = pcicfgr16(p, PciCCRu);
1999/0301    
			p->ccrp = pcicfgr8(p, PciCCRp); 
			p->ccru = pcicfgr8(p, PciCCRu); 
			p->ccrb = pcicfgr8(p, PciCCRb);
1997/0327    
1998/0312    
			/* 
			 * If the device is a multi-function device adjust the
1998/1121/sys/src/9/pc/pci.c:83,95 – 1999/0301/sys/src/9/pc/pci.c:238,249
1998/0312    
			 * If appropriate, read the base address registers 
			 * and work out the sizes. 
			 */ 
			switch(p->ccru>>8){ 
                 
1999/0301    
			switch(p->ccrb) {
1998/0312    
			case 0x01:		/* mass storage controller */ 
			case 0x02:		/* network controller */ 
			case 0x03:		/* display controller */ 
			case 0x04:		/* multimedia device */ 
			case 0x07:		/* simple communication controllers */
1999/0301    
			case 0x07:		/* simple comm. controllers */
1998/0312    
			case 0x08:		/* base system peripherals */ 
			case 0x09:		/* input devices */ 
			case 0x0A:		/* docking stations */
1998/1121/sys/src/9/pc/pci.c:98,110 – 1999/0301/sys/src/9/pc/pci.c:252,261
1998/0312    
				if((hdt & 0x7F) != 0) 
					break; 
				rno = PciBAR0 - 4; 
				for(i = 0; i < nelem(p->mem); i++){
1999/0301    
				for(i = 0; i < nelem(p->mem); i++) {
1998/0312    
					rno += 4; 
					p->mem[i].bar = pcicfgr32(p, rno); 
					pcicfgw32(p, rno, -1); 
					v = pcicfgr32(p, rno); 
					pcicfgw32(p, rno, p->mem[i].bar); 
					p->mem[i].size = -(v & ~0xF);
1999/0301    
					p->mem[i].size = pcibarsize(p, rno);
1998/0312    
				} 
				break;
1998/1121/sys/src/9/pc/pci.c:128,153 – 1999/0301/sys/src/9/pc/pci.c:279,305
1997/0327    
		/*
1998/0312    
		 * Find PCI-PCI bridges and recursively descend the tree.
1997/0327    
		 */
1997/1011    
		if(p->ccru != ((0x06<<8)|0x04))
1999/0301    
		if(p->ccrb != 0x06 || p->ccru != 0x04)
1997/1011    
			continue;
1995/0725    
1997/0327    
		/* 
		 * If the secondary or subordinate bus number is not initialised 
		 * try to do what the PCI BIOS should have done and fill in the 
		 * numbers as the tree is descended. On the way down the subordinate 
		 * bus number is set to the maximum as it's not known how many 
		 * buses are behind this one; the final value is set on the way 
		 * back up.
1999/0301    
		 * If the secondary or subordinate bus number is not 
		 * initialised try to do what the PCI BIOS should have 
		 * done and fill in the numbers as the tree is descended. 
		 * On the way down the subordinate bus number is set to 
		 * the maximum as it's not known how many buses are behind 
		 * this one; the final value is set on the way back up.
1997/0327    
		 */
1998/0312    
		sbn = pcicfgr8(p, PciSBN); 
		ubn = pcicfgr8(p, PciUBN);
1997/0327    
		if(sbn == 0 || ubn == 0){
1999/0301    
 
		if(sbn == 0 || ubn == 0 || NOBIOS) {
1997/0327    
			sbn = maxubn+1; 
			/* 
			 * Make sure memory, I/O and master enables are off, 
			 * set the primary, secondary and subordinate bus numbers 
			 * and clear the secondary status before attempting to 
			 * scan the secondary bus.
1999/0301    
			 * Make sure memory, I/O and master enables are 
			 * off, set the primary, secondary and subordinate 
			 * bus numbers and clear the secondary status before 
			 * attempting to scan the secondary bus.
1997/0327    
			 * 
			 * Initialisation of the bridge should be done here. 
			 */
1998/1121/sys/src/9/pc/pci.c:157,173 – 1999/0301/sys/src/9/pc/pci.c:309,354
1998/0312    
			pcicfgw16(p, PciSPSR, 0xFFFF);
1997/1011    
			maxubn = pciscan(sbn, &p->bridge);
1997/0327    
			l = (maxubn<<16)|(sbn<<8)|bno;
1999/0301    
1998/0312    
			pcicfgw32(p, PciPBN, l);
1997/0327    
		} 
		else{
1999/0301    
		else {
1997/0327    
			maxubn = ubn;
1997/1011    
			pciscan(sbn, &p->bridge);
1997/0327    
		}
1999/0301    
 
		/* 
		 * Now figure out the size of things below the bridge 
		 */ 
		if(NOBIOS) { 
			mema = 0; 
			ioa = 0; 
			pcibusmap(p->bridge, &mema, &ioa, 0); 
			p->mem[BARmem].size = ROUND(mema, 1<<20); 
			p->mem[BARio].size = ROUND(ioa, 1<<12); 
		}
1995/0725    
	}
1997/0327    
	return maxubn;
1995/0725    
}
1999/0301    
static ulong 
pcimask(ulong v) 
{ 
	ulong m; 
 
	if(!NOBIOS) 
		return 0; 
 
	m = BI2BY*sizeof(v); 
	for(m = 1<<(m-1); m != 0; m >>= 1) { 
		if(m & v) 
			break; 
	} 
	v |= m-1; 
	return v+1; 
}
1997/0327    
static void 
pcicfginit(void)
1995/0517    
{
1998/1121/sys/src/9/pc/pci.c:174,216 – 1999/0301/sys/src/9/pc/pci.c:355,426
1998/0312    
	char *p; 
	int bno; 
	Pcidev **list;
1999/0301    
	ulong mema, ioa, size;
1998/0312    
1997/0327    
	lock(&pcicfginitlock); 
	if(pcicfgmode == -1){
1999/0301    
	if(pcicfgmode != -1) 
		goto out; 
 
	/* 
	 * Try to determine which PCI configuration mode is implemented. 
	 * Mode2 uses a byte at 0xCF8 and another at 0xCFA; Mode1 uses 
	 * a DWORD at 0xCF8 and another at 0xCFC and will pass through 
	 * any non-DWORD accesses as normal I/O cycles. There shouldn't be 
	 * a device behind these addresses so if Mode2 accesses fail try 
	 * for Mode1 (which is preferred, Mode2 is deprecated). 
	 */ 
	outb(PciCSE, 0); 
	if(inb(PciCSE) == 0){ 
		pcicfgmode = 2; 
		pcimaxdno = 15; 
	} 
	else { 
		outl(PciADDR, 0); 
		if(inl(PciADDR) == 0){ 
			pcicfgmode = 1; 
			pcimaxdno = 31; 
		} 
	} 
	 
	if(pcicfgmode < 0) 
		goto out; 
 
	if(p = getconf("*pcimaxdno")) 
		pcimaxdno = strtoul(p, 0, 0); 
 
	list = &pciroot; 
	for(bno = 0; bno < 256; bno++) { 
		bno = pciscan(bno, list); 
		while(*list) 
			list = &(*list)->link; 
	} 
 
	if(NOBIOS){
1997/0327    
		/* 
		 * Try to determine which PCI configuration mode is implemented. 
		 * Mode2 uses a byte at 0xCF8 and another at 0xCFA; Mode1 uses 
		 * a DWORD at 0xCF8 and another at 0xCFC and will pass through 
		 * any non-DWORD accesses as normal I/O cycles. There shouldn't be
1998/0312    
		 * a device behind these addresses so if Mode2 accesses fail try
1997/0327    
		 * for Mode1 (which is preferred, Mode2 is deprecated).
1999/0301    
		 * Work out how big the top bus is
1997/0327    
		 */ 
		outb(PciCSE, 0); 
		if(inb(PciCSE) == 0){ 
			pcicfgmode = 2;
1997/0329    
			pcimaxdno = 15;
1997/0327    
		} 
		else{ 
			outl(PciADDR, 0); 
			if(inl(PciADDR) == 0){ 
				pcicfgmode = 1;
1997/0329    
				pcimaxdno = 31;
1997/0327    
			} 
		}
1999/0301    
		mema = 0; 
		ioa = 0; 
		pcibusmap(pciroot, &mema, &ioa, 0);
1997/0327    
1998/0312    
		if(pcicfgmode > 0){ 
			if(p = getconf("*pcimaxdno")) 
				pcimaxdno = strtoul(p, 0, 0);
1999/0301    
		print("Sizes: mem=%lux io=%lux\n", mema, ioa); 
	 
		/* 
		 * Align the windows and map it 
		 */ 
		size = pcimask(mema); 
		mema = (0xFE000000 & ~(size-1)) - size; 
		size = pcimask(ioa); 
		ioa = (0xFE00 & ~(size-1)) - size; 
	 
		pcibusmap(pciroot, &mema, &ioa, 1); 
	 
		unlock(&pcicfginitlock); 
		pcihinv(nil);
1998/0312    
 
			list = &pciroot; 
			for(bno = 0; bno < 256; bno++){ 
				bno = pciscan(bno, list);
1998/0324    
				while(*list)
1998/0312    
					list = &(*list)->link; 
			} 
				                 
		}
1999/0301    
		return;
1997/0327    
	}
1999/0301    
out:
1997/0327    
	unlock(&pcicfginitlock); 
}
1995/0517    
1998/1121/sys/src/9/pc/pci.c:396,402 – 1999/0301/sys/src/9/pc/pci.c:606,613
1997/1011    
		prev = prev->list;
1997/0327    
1998/0906    
	while(prev != nil){
1998/1121    
		if((vid == 0 || prev->vid == vid) && (did == 0 || prev->did == did))
1999/0301    
		if((vid == 0 || prev->vid == vid) 
		&& (did == 0 || prev->did == did))
1997/0327    
			break;
1997/1011    
		prev = prev->list;
1995/0721    
	}
1998/1121/sys/src/9/pc/pci.c:411,417 – 1999/0301/sys/src/9/pc/pci.c:622,628
1998/0906    
	if(pcicfgmode == -1) 
		pcicfginit(); 
 
	for(pcidev = pcilist; pcidev != nil; pcidev = pcidev->list){
1999/0301    
	for(pcidev = pcilist; pcidev != nil; pcidev = pcidev->list) {
1998/0906    
		if(pcidev->tbdf == tbdf) 
			break; 
	}
1998/1121/sys/src/9/pc/pci.c:429,437 – 1999/0301/sys/src/9/pc/pci.c:640,648
1998/0322    
		print("bus dev type vid  did intl memory\n");
1997/1011    
	} 
	for(t = p; t != nil; t = t->link) {
1998/0322    
		print("%d  %2d/%d %.4ux %.4ux %.4ux %2d  ",
1999/0301    
		print("%d  %2d/%d %.2ux %.2ux %.2ux %.4ux %.4ux %2d  ",
1997/1011    
			BUSBNO(t->tbdf), BUSDNO(t->tbdf), BUSFNO(t->tbdf),
1998/0108    
			t->ccru, t->vid, t->did, t->intl);
1999/0301    
			t->ccrb, t->ccru, t->ccrp, t->vid, t->did, t->intl);
1997/1011    
 
		for(i = 0; i < nelem(p->mem); i++) { 
			if(t->mem[i].size == 0)
1999/0301/sys/src/9/pc/pci.c:669,675 – 1999/0314/sys/src/9/pc/pci.c:669,686 (short | long)
1998/0108    
		pcicfginit(); 
 
	for(p = pcilist; p != nil; p = p->list){ 
		pcr = pcicfgr16(p, PciPSR); 
		pcicfgw16(p, PciPSR, pcr & ~0x04);
1999/0314    
		pcr = pcicfgr16(p, PciPCR); 
		pcr &= ~0x0004; 
		pcicfgw16(p, PciPCR, pcr);
1998/0108    
	}
1999/0314    
} 
 
void 
pcisetbme(Pcidev* p) 
{ 
	int pcr; 
 
	pcr = pcicfgr16(p, PciPCR); 
	pcr |= 0x0004; 
	pcicfgw16(p, PciPCR, pcr);
1995/0517    
}
1999/0314/sys/src/9/pc/pci.c:188,194 – 1999/0620/sys/src/9/pc/pci.c:188,193 (short | long)
1997/0327    
static int 
pciscan(int bno, Pcidev** list)
1995/0725    
{
1999/0301    
	ulong mema, ioa;
1997/0327    
	Pcidev *p, *head, *tail;
1998/0312    
	int dno, fno, i, hdt, l, maxfno, maxubn, rno, sbn, tbdf, ubn;
1997/0327    
1999/0620/sys/src/9/pc/pci.c:9,14 – 1999/0622/sys/src/9/pc/pci.c:9,38 (short | long)
1995/0517    
#include "io.h" 
#include "../port/error.h"
1999/0622    
#define DBG	if(0) pcilog 
 
struct 
{ 
	char	output[16384]; 
	int	ptr; 
}PCICONS; 
 
int 
pcilog(char *fmt, ...) 
{ 
	int n; 
	va_list arg; 
	char buf[PRINTSIZE]; 
 
	va_start(arg, fmt); 
	n = doprint(buf, buf+sizeof(buf), fmt, arg) - buf; 
	va_end(arg); 
 
	memmove(PCICONS.output+PCICONS.ptr, buf, n); 
	PCICONS.ptr += n; 
	return n; 
}
1999/0301    
enum 
{					/* configuration mechanism #1 */
1997/0327    
	PciADDR		= 0xCF8,	/* CONFIG_ADDRESS */
1999/0620/sys/src/9/pc/pci.c:21,33 – 1999/0622/sys/src/9/pc/pci.c:45,55
1997/0327    
	MaxFNO		= 7, 
	MaxUBN		= 255,
1999/0301    
 
	BARio		= 0,		/* fake BAR registers for bridges */ 
	BARmem, 
                 
	NOBIOS		= 0,		/* initialise if the BIOS didn't */
1997/0327    
};
1999/0301    
enum {					/* command register */
1999/0622    
enum 
{					/* command register */
1999/0301    
	IOen		= (1<<0), 
	MEMen		= (1<<1), 
	MASen		= (1<<2),
1999/0620/sys/src/9/pc/pci.c:47,52 – 1999/0622/sys/src/9/pc/pci.c:69,131
1997/0327    
static int pcicfgrw32(int, int, int, int);
1999/0301    
static int pcicfgrw8(int, int, int, int);
1997/0327    
1999/0622    
static char* bustypes[] = { 
	"CBUSI", 
	"CBUSII", 
	"EISA", 
	"FUTURE", 
	"INTERN", 
	"ISA", 
	"MBI", 
	"MBII", 
	"MCA", 
	"MPI", 
	"MPSA", 
	"NUBUS", 
	"PCI", 
	"PCMCIA", 
	"TC", 
	"VL", 
	"VME", 
	"XPRESS", 
}; 
 
#pragma	varargck	type	"T"	int 
 
static int 
tbdfconv(va_list* arg, Fconv* f) 
{ 
	char *p; 
	int l, type, tbdf; 
 
	p = malloc(READSTR); 
	if(p == nil){ 
		strconv("(tbdfconv)", f); 
		return sizeof(int); 
	} 
		 
	switch(f->chr){ 
	case 'T': 
		tbdf = va_arg(*arg, int); 
		type = BUSTYPE(tbdf); 
		if(type < nelem(bustypes)) 
			l = snprint(p, READSTR, bustypes[type]); 
		else 
			l = snprint(p, READSTR, "%d", type); 
		snprint(p+l, READSTR-l, ".%d.%d.%d", 
			BUSBNO(tbdf), BUSDNO(tbdf), BUSFNO(tbdf)); 
		break; 
 
	default: 
		snprint(p, READSTR, "(tbdfconv)"); 
		break; 
	} 
	strconv(p, f); 
	free(p); 
 
	return sizeof(int); 
}
1999/0301    
ulong 
pcibarsize(Pcidev *p, int rno) 
{
1999/0620/sys/src/9/pc/pci.c:62,188 – 1999/0622/sys/src/9/pc/pci.c:141,361
1999/0301    
	return -(size & ~0x0F); 
}
1999/0622    
static int 
pcisizcmp(void* va, void* vb) 
{ 
	Pcisiz *a, *b; 
 
	a = va; 
	b = vb; 
	return a->siz - b->siz; 
} 
 
static ulong 
pcimask(ulong v) 
{ 
	ulong m; 
 
	m = BI2BY*sizeof(v); 
	for(m = 1<<(m-1); m != 0; m >>= 1) { 
		if(m & v) 
			break; 
	} 
 
	m--; 
	if((v & m) == 0) 
		return v; 
 
	v |= m; 
	return v+1; 
}
1999/0301    
static void 
pcibusmap(Pcidev *p, ulong *pmema, ulong *pioa, int wrreg)
1999/0622    
pcibusmap(Pcidev *root, ulong *pmema, ulong *pioa, int wrreg)
1999/0301    
{ 
	int i, size, k; 
	ulong addr, v, mema, ioa, pcr, tmema, tioa;
1999/0622    
	Pcidev *p; 
	int ntb, i, size, rno, hole; 
	ulong v, mema, ioa, sioa, smema, base, limit; 
	Pcisiz *table, *tptr, *mtb, *itb; 
	extern void qsort(void*, long, long, int (*)(void*, void*));
1999/0301    
 
	if(!NOBIOS) 
		return; 
 
	mema = *pmema; 
	ioa = *pioa;
1999/0622    
	mema = *pmema;
1999/0301    
 
	print("pcibusmap wr=%d %d.%d.%d mem=%lux io=%lux\n",  
		wrreg, BUSBNO(p->tbdf), BUSDNO(p->tbdf), BUSFNO(p->tbdf), 
		mema, ioa);
1999/0622    
	DBG("pcibusmap wr=%d %T mem=%lux io=%lux\n",  
		wrreg, root->tbdf, mema, ioa);
1999/0301    
1999/0622    
	ntb = 0; 
	for(p = root; p != nil; p = p->link) 
		ntb++; 
 
	ntb *= (PciCIS-PciBAR0)/4; 
	table = malloc(2*ntb*sizeof(Pcisiz)); 
	itb = table; 
	mtb = table+ntb;
1999/0301    
	/* 
	 * Allocate address space on this bus 
	 * note this loop follows link, not list
1999/0622    
	 * Build a table of sizes
1999/0301    
	 */ 
	for(; p; p = p->link) {
1999/0622    
	for(p = root; p != nil; p = p->link) {
1999/0301    
		if(p->ccrb == 0x06) { 
			if(p->ccru != 0x04) { 
				print("pci: ignored bridge %d.%d.%d\n", 
					BUSBNO(p->tbdf), 
					BUSDNO(p->tbdf), 
					BUSFNO(p->tbdf));
1999/0622    
			if(p->ccru != 0x04 || p->bridge == nil) { 
//				DBG("pci: ignored bridge %T\n", p->tbdf);
1999/0301    
				continue; 
			} 
 
			/* Base */ 
			p->mem[BARio].bar = ioa; 
			p->mem[BARmem].bar = mema; 
			tioa = ioa; 
			tmema = mema;
1999/0622    
			sioa = ioa; 
			smema = mema; 
			pcibusmap(p->bridge, &smema, &sioa, 0);
1999/0301    
 
			/* Limit */ 
			ioa += p->mem[BARio].size; 
			mema += p->mem[BARmem].size;
1999/0622    
			hole = pcimask(smema-mema); 
			if(hole < (1<<20)) 
				hole = 1<<20; 
			p->mema.size = hole;
1999/0301    
 
			if(wrreg == 0) 
				continue;
1999/0622    
			hole = pcimask(sioa-ioa); 
			if(hole < (1<<12)) 
				hole = 1<<12;
1999/0301    
 
			pcibusmap(p->bridge, &tmema, &tioa, 1);
1999/0622    
			p->ioa.size = hole;
1999/0301    
 
			/* 
			 * IO base[15:12], IO limit [15:12] 
			 */ 
			v =	(0xFFFF<<16)| 
				(ioa & 0xF000)| 
				((p->mem[BARio].bar & 0xF000)>>8);
1999/0622    
			itb->dev = p; 
			itb->bar = -1; 
			itb->siz = p->ioa.size; 
			itb++;
1999/0301    
 
			pcicfgrw32(p->tbdf, PciBAR3, v, 0); 
                 
			/* 
			 * Memory Base/Limit 
			 */ 
			v =	(mema & ~((1<<20)-1)) | 
				((p->mem[BARmem].bar & ~((1<<20)-1)) >> 16); 
                 
			pcicfgrw32(p->tbdf, PciBAR4, v, 0); 
                 
			/* 
			 * Disable memory prefetch 
			 */ 
			pcicfgrw32(p->tbdf, PciBAR5, 0x0000FFFF, 0); 
                 
			/* 
			 * Enable the bridge 
			 */ 
			v = 0xFFFF0000 | IOen | MEMen | MASen; 
			pcicfgrw32(p->tbdf, PciPCR, v, 0);
1999/0622    
			mtb->dev = p; 
			mtb->bar = -1; 
			mtb->siz = p->mema.size; 
			mtb++;
1999/0301    
			continue; 
		} 
 
		pcr = pcicfgrw32(p->tbdf, PciPCR, 0, 1); 
		                 
		for(i = PciBAR0; i <= PciBAR5; i += 4) { 
			v = pcicfgrw32(p->tbdf, i, 0, 1); 
			size = pcibarsize(p, i); 
			if(size > 16*1024*1024) 
				print("pcimap: size %d?\n", size);
1999/0622    
		for(i = 0; i <= 5; i++) { 
			rno = PciBAR0 + i*4; 
			v = pcicfgrw32(p->tbdf, rno, 0, 1); 
			size = pcibarsize(p, rno);
1999/0301    
			if(size == 0) 
				continue; 
 
			if(v & 1) {		/* Allocate IO space */ 
				ioa = (ioa+size-1) & ~(size-1); 
				addr = ioa; 
				ioa += size; 
				pcr |= IOen;
1999/0622    
			if(v & 1) { 
				itb->dev = p; 
				itb->bar = i; 
				itb->siz = size; 
				itb++;
1999/0301    
			} 
			else {			/* Allocate Memory space */ 
				mema = (mema+size-1) & ~(size-1); 
				addr = mema; 
				mema += size; 
				pcr |= MEMen;
1999/0622    
			else { 
				mtb->dev = p; 
				mtb->bar = i; 
				mtb->siz = size; 
				mtb++;
1999/0301    
			} 
 
			k = (i-PciBAR0)/4; 
			p->mem[k].size = size; 
			p->mem[k].bar = addr; 
			if(wrreg) 
				pcicfgrw32(p->tbdf, i, addr, 0);
1999/0622    
			p->mem[i].size = size;
1999/0301    
		}
1999/0622    
	}
1999/0301    
 
		/* 
		 * Set latency timer 
		 * Enable memory/io/master 
		 */ 
		if(wrreg) { 
			pcicfgrw8(p->tbdf, PciLTR, 64, 0);
1999/0622    
	/* 
	 * Sort both tables IO smallest first, Memory largest 
	 */ 
	qsort(table, itb-table, sizeof(Pcisiz), pcisizcmp); 
	tptr = table+ntb; 
	qsort(tptr, mtb-tptr, sizeof(Pcisiz), pcisizcmp);
1999/0301    
 
			pcr |= MASen; 
			pcicfgrw32(p->tbdf, PciPCR, pcr, 0);
1999/0622    
	/* 
	 * Allocate IO address space on this bus 
	 */ 
	for(tptr = table; tptr < itb; tptr++) { 
		hole = tptr->siz; 
		if(tptr->bar == -1) 
			hole = 1<<12; 
		ioa = (ioa+hole-1) & ~(hole-1); 
 
		p = tptr->dev; 
		if(tptr->bar == -1) 
			p->ioa.bar = ioa; 
		else { 
			p->pcr |= IOen; 
			p->mem[tptr->bar].bar = ioa|1; 
			if(wrreg) 
				pcicfgrw32(p->tbdf, PciBAR0+(tptr->bar*4), ioa|1, 0);
1999/0301    
		}
1999/0622    
 
		ioa += tptr->siz;
1999/0301    
	} 
 
	print("pcibusmap mem=%lux io=%lux\n", mema, ioa);
1999/0622    
	/* 
	 * Allocate Memory address space on this bus 
	 */ 
	for(tptr = table+ntb; tptr < mtb; tptr++) { 
		hole = tptr->siz; 
		if(tptr->bar == -1) 
			hole = 1<<20; 
		mema = (mema+hole-1) & ~(hole-1);
1999/0301    
1999/0622    
		p = tptr->dev; 
		if(tptr->bar == -1) 
			p->mema.bar = mema; 
		else { 
			p->pcr |= MEMen; 
			p->mem[tptr->bar].bar = mema; 
			if(wrreg) 
				pcicfgrw32(p->tbdf, PciBAR0+(tptr->bar*4), mema, 0); 
		} 
		mema += tptr->siz; 
	}
1999/0301    
	*pmema = mema; 
	*pioa = ioa;
1999/0622    
	free(table); 
 
	if(wrreg == 0) 
		return; 
 
	/* 
	 * Finally set all the bridge addresses & registers 
	 */ 
	for(p = root; p != nil; p = p->link) { 
		if(p->bridge == nil) { 
			pcicfgrw8(p->tbdf, PciLTR, 64, 0); 
 
			p->pcr |= MASen; 
			pcicfgrw32(p->tbdf, PciPCR, p->pcr, 0); 
			continue; 
		} 
 
		base = p->ioa.bar; 
		limit = base+p->ioa.size-1; 
		v = pcicfgrw32(p->tbdf, PciBAR3, 0, 1); 
		v = (v&0xFFFF0000)|(limit & 0xF000)|((base & 0xF000)>>8); 
		pcicfgrw32(p->tbdf, PciBAR3, v, 0); 
		v = (limit & 0xFFFF0000)|(base>>16); 
		pcicfgrw32(p->tbdf, 0x30, v, 0); 
 
		base = p->mema.bar; 
		limit = base+p->mema.size-1; 
		v = (limit & 0xFFF00000)|((base & 0xFFF00000)>>16); 
		pcicfgrw32(p->tbdf, PciBAR4, v, 0); 
 
		/* 
		 * Disable memory prefetch 
		 */ 
		pcicfgrw32(p->tbdf, PciBAR5, 0x0000FFFF, 0); 
		pcicfgrw8(p->tbdf, PciLTR, 64, 0); 
 
		/* 
		 * Enable the bridge 
		 */ 
		v = 0xFFFF0000 | IOen | MEMen | MASen; 
		pcicfgrw32(p->tbdf, PciPCR, v, 0); 
 
		sioa = p->ioa.bar; 
		smema = p->mema.bar; 
		pcibusmap(p->bridge, &smema, &sioa, 1); 
	}
1999/0301    
}
1997/0327    
static int
1999/0620/sys/src/9/pc/pci.c:224,229 – 1999/0622/sys/src/9/pc/pci.c:397,403
1999/0301    
			p->ccrp = pcicfgr8(p, PciCCRp); 
			p->ccru = pcicfgr8(p, PciCCRu); 
			p->ccrb = pcicfgr8(p, PciCCRb);
1999/0622    
			p->pcr = pcicfgr32(p, PciPCR);
1997/0327    
1998/0312    
			/* 
			 * If the device is a multi-function device adjust the
1999/0620/sys/src/9/pc/pci.c:315,353 – 1999/0622/sys/src/9/pc/pci.c:489,499
1997/0327    
			maxubn = ubn;
1997/1011    
			pciscan(sbn, &p->bridge);
1997/0327    
		}
1999/0301    
                 
		/* 
		 * Now figure out the size of things below the bridge 
		 */ 
		if(NOBIOS) { 
			mema = 0; 
			ioa = 0; 
			pcibusmap(p->bridge, &mema, &ioa, 0); 
			p->mem[BARmem].size = ROUND(mema, 1<<20); 
			p->mem[BARio].size = ROUND(ioa, 1<<12); 
		}
1995/0725    
	}
1997/0327    
	return maxubn;
1995/0725    
}
1999/0301    
static ulong 
pcimask(ulong v) 
{ 
	ulong m; 
                 
	if(!NOBIOS) 
		return 0; 
                 
	m = BI2BY*sizeof(v); 
	for(m = 1<<(m-1); m != 0; m >>= 1) { 
		if(m & v) 
			break; 
	} 
	v |= m-1; 
	return v+1; 
} 
                 
1997/0327    
static void 
pcicfginit(void)
1995/0517    
{
1999/0620/sys/src/9/pc/pci.c:354,360 – 1999/0622/sys/src/9/pc/pci.c:500,506
1998/0312    
	char *p; 
	int bno; 
	Pcidev **list;
1999/0301    
	ulong mema, ioa, size;
1999/0622    
	ulong mema, ioa;
1998/0312    
1997/0327    
	lock(&pcicfginitlock);
1999/0301    
	if(pcicfgmode != -1)
1999/0620/sys/src/9/pc/pci.c:384,389 – 1999/0622/sys/src/9/pc/pci.c:530,537
1999/0301    
	if(pcicfgmode < 0) 
		goto out;
1999/0622    
	fmtinstall('T', tbdfconv);
1999/0301    
	if(p = getconf("*pcimaxdno")) 
		pcimaxdno = strtoul(p, 0, 0);
1999/0620/sys/src/9/pc/pci.c:394,400 – 1999/0622/sys/src/9/pc/pci.c:542,551
1999/0301    
			list = &(*list)->link; 
	} 
 
	if(NOBIOS){
1999/0622    
	if(pciroot == nil) 
		goto out; 
 
	if(NOBIOS) {
1997/0327    
		/*
1999/0301    
		 * Work out how big the top bus is
1997/0327    
		 */
1999/0620/sys/src/9/pc/pci.c:401,422 – 1999/0622/sys/src/9/pc/pci.c:552,572
1999/0301    
		mema = 0; 
		ioa = 0; 
		pcibusmap(pciroot, &mema, &ioa, 0);
1999/0622    
 
DBG("Sizes: mem=%8.8lux size=%8.8lux io=%8.8lux\n", mema, pcimask(mema), ioa);
1997/0327    
1999/0301    
		print("Sizes: mem=%lux io=%lux\n", mema, ioa); 
	                 
		/* 
		 * Align the windows and map it 
		 */ 
		size = pcimask(mema); 
		mema = (0xFE000000 & ~(size-1)) - size; 
		size = pcimask(ioa); 
		ioa = (0xFE00 & ~(size-1)) - size; 
	                 
1999/0622    
		ioa = 0x1000; 
		mema = 0x90000000; 
 
		pcilog("Mask sizes: mem=%lux io=%lux\n", mema, ioa);
1999/0301    
		pcibusmap(pciroot, &mema, &ioa, 1);
1999/0622    
DBG("Sizes2: mem=%lux io=%lux\n", mema, ioa);
1999/0301    
	 
		unlock(&pcicfginitlock); 
		pcihinv(nil);
1998/0312    
                 
1999/0301    
		return;
1997/0327    
	}
1999/0301    
out:
1999/0620/sys/src/9/pc/pci.c:635,645 – 1999/0622/sys/src/9/pc/pci.c:785,796
1997/1011    
	Pcidev *t; 
 
	if(p == nil) {
1999/0622    
putstrn(PCICONS.output, PCICONS.ptr);
1997/1011    
		p = pciroot;
1998/0322    
		print("bus dev type vid  did intl memory\n");
1997/1011    
	} 
	for(t = p; t != nil; t = t->link) {
1999/0301    
		print("%d  %2d/%d %.2ux %.2ux %.2ux %.4ux %.4ux %2d  ",
1999/0622    
		print("%d  %2d/%d %.2ux %.2ux %.2ux %.4ux %.4ux %3d  ",
1997/1011    
			BUSBNO(t->tbdf), BUSDNO(t->tbdf), BUSFNO(t->tbdf),
1999/0301    
			t->ccrb, t->ccru, t->ccrp, t->vid, t->did, t->intl);
1997/1011    
1999/0620/sys/src/9/pc/pci.c:649,661 – 1999/0622/sys/src/9/pc/pci.c:800,823
1997/1011    
			print("%d:%.8lux %d ", i, 
				t->mem[i].bar, t->mem[i].size); 
		}
1999/0622    
		if(t->ioa.bar || t->ioa.size) 
			print("ioa:%.8lux %d ", t->ioa.bar, t->ioa.size); 
		if(t->mema.bar || t->mema.size) 
			print("mema:%.8lux %d ", t->mema.bar, t->mema.size); 
		if(t->bridge) 
			print("->%d", BUSBNO(t->bridge->tbdf));
1997/1011    
		print("\n"); 
	}
1999/0622    
#define notdef 
#ifdef notdef
1997/1011    
	while(p != nil) { 
		if(p->bridge != nil) 
			pcihinv(p->bridge); 
		p = p->link;
1997/0327    
	}
1999/0622    
#else 
print("more...\n"); 
#endif /* notdef */
1998/0108    
} 
 
void
1999/0620/sys/src/9/pc/pci.c:680,685 – 1999/0622/sys/src/9/pc/pci.c:842,847
1999/0314    
	int pcr; 
 
	pcr = pcicfgr16(p, PciPCR); 
	pcr |= 0x0004;
1999/0622    
	pcr |= MASen;
1999/0314    
	pcicfgw16(p, PciPCR, pcr);
1995/0517    
}
1999/0622/sys/src/9/pc/pci.c:142,154 – 2000/0506/sys/src/9/pc/pci.c:142,154 (short | long)
1999/0301    
}
1999/0622    
static int 
pcisizcmp(void* va, void* vb)
2000/0506    
pcisizcmp(void *a, void *b)
1999/0622    
{ 
	Pcisiz *a, *b;
2000/0506    
	Pcisiz *aa, *bb;
1999/0622    
 
	a = va; 
	b = vb; 
	return a->siz - b->siz;
2000/0506    
	aa = a; 
	bb = b; 
	return aa->siz - bb->siz;
1999/0622    
} 
 
static ulong
1999/0622/sys/src/9/pc/pci.c:185,191 – 2000/0506/sys/src/9/pc/pci.c:185,191
1999/0301    
	ioa = *pioa;
1999/0622    
	mema = *pmema;
1999/0301    
1999/0622    
	DBG("pcibusmap wr=%d %T mem=%lux io=%lux\n",
2000/0506    
	DBG("pcibusmap wr=%d %T mem=%luX io=%luX\n",
1999/0622    
		wrreg, root->tbdf, mema, ioa);
1999/0301    
1999/0622    
	ntb = 0;
1999/0622/sys/src/9/pc/pci.c:202,208 – 2000/0506/sys/src/9/pc/pci.c:202,209
1999/0301    
	 */
1999/0622    
	for(p = root; p != nil; p = p->link) {
1999/0301    
		if(p->ccrb == 0x06) {
1999/0622    
			if(p->ccru != 0x04 || p->bridge == nil) {
2000/0506    
			if((p->ccru != 0x04 && p->ccru != 0x07) 
			|| p->bridge == nil) {
1999/0622    
//				DBG("pci: ignored bridge %T\n", p->tbdf);
1999/0301    
				continue; 
			}
1999/0622/sys/src/9/pc/pci.c:393,404 – 2000/0506/sys/src/9/pc/pci.c:394,407
1997/1101    
				pcilist = p; 
			pcitail = p;
1997/1011    
1998/0312    
			p->intl = pcicfgr8(p, PciINTL);
2000/0506    
			p->rid = pcicfgr8(p, PciRID);
1999/0301    
			p->ccrp = pcicfgr8(p, PciCCRp); 
			p->ccru = pcicfgr8(p, PciCCRu); 
			p->ccrb = pcicfgr8(p, PciCCRb);
1999/0622    
			p->pcr = pcicfgr32(p, PciPCR);
1997/0327    
2000/0506    
			p->intl = pcicfgr8(p, PciINTL);
1998/0312    
			/* 
			 * If the device is a multi-function device adjust the 
			 * loop count so all possible functions are checked.
1999/0622/sys/src/9/pc/pci.c:452,458 – 2000/0506/sys/src/9/pc/pci.c:455,461
1997/0327    
		/*
1998/0312    
		 * Find PCI-PCI bridges and recursively descend the tree.
1997/0327    
		 */
1999/0301    
		if(p->ccrb != 0x06 || p->ccru != 0x04)
2000/0506    
		if(p->ccrb != 0x06 || (p->ccru != 0x04 && p->ccru != 0x07))
1997/1011    
			continue;
1995/0725    
1997/0327    
		/*
1999/0622/sys/src/9/pc/pci.c:553,559 – 2000/0506/sys/src/9/pc/pci.c:556,563
1999/0301    
		ioa = 0; 
		pcibusmap(pciroot, &mema, &ioa, 0);
1999/0622    
 
DBG("Sizes: mem=%8.8lux size=%8.8lux io=%8.8lux\n", mema, pcimask(mema), ioa);
2000/0506    
		DBG("Sizes: mem=%8.8lux size=%8.8lux io=%8.8lux\n", 
			mema, pcimask(mema), ioa);
1997/0327    
1999/0301    
		/* 
		 * Align the windows and map it
1999/0622/sys/src/9/pc/pci.c:564,570 – 2000/0506/sys/src/9/pc/pci.c:568,574
1999/0622    
		pcilog("Mask sizes: mem=%lux io=%lux\n", mema, ioa);
1999/0301    
		pcibusmap(pciroot, &mema, &ioa, 1);
1999/0622    
DBG("Sizes2: mem=%lux io=%lux\n", mema, ioa);
2000/0506    
		DBG("Sizes2: mem=%lux io=%lux\n", mema, ioa);
1999/0301    
	 
		unlock(&pcicfginitlock); 
		return;
1999/0622/sys/src/9/pc/pci.c:785,791 – 2000/0506/sys/src/9/pc/pci.c:789,795
1997/1011    
	Pcidev *t; 
 
	if(p == nil) {
1999/0622    
putstrn(PCICONS.output, PCICONS.ptr);
2000/0506    
		putstrn(PCICONS.output, PCICONS.ptr);
1997/1011    
		p = pciroot;
1998/0322    
		print("bus dev type vid  did intl memory\n");
1997/1011    
	}
1999/0622/sys/src/9/pc/pci.c:808,823 – 2000/0506/sys/src/9/pc/pci.c:812,822
1999/0622    
			print("->%d", BUSBNO(t->bridge->tbdf));
1997/1011    
		print("\n"); 
	}
1999/0622    
#define notdef 
#ifdef notdef
1997/1011    
	while(p != nil) { 
		if(p->bridge != nil) 
			pcihinv(p->bridge); 
		p = p->link;
1997/0327    
	}
1999/0622    
#else 
print("more...\n"); 
#endif /* notdef */
1998/0108    
} 
 
void
2000/0506/sys/src/9/pc/pci.c:202,209 – 2000/0517/sys/src/9/pc/pci.c:202,208 (short | long)
1999/0301    
	 */
1999/0622    
	for(p = root; p != nil; p = p->link) {
1999/0301    
		if(p->ccrb == 0x06) {
2000/0506    
			if((p->ccru != 0x04 && p->ccru != 0x07) 
			|| p->bridge == nil) {
2000/0517    
			if(p->ccru != 0x04 || p->bridge == nil) {
1999/0622    
//				DBG("pci: ignored bridge %T\n", p->tbdf);
1999/0301    
				continue; 
			}
2000/0506/sys/src/9/pc/pci.c:455,461 – 2000/0517/sys/src/9/pc/pci.c:454,460
1997/0327    
		/*
1998/0312    
		 * Find PCI-PCI bridges and recursively descend the tree.
1997/0327    
		 */
2000/0506    
		if(p->ccrb != 0x06 || (p->ccru != 0x04 && p->ccru != 0x07))
2000/0517    
		if(p->ccrb != 0x06 || p->ccru != 0x04)
1997/1011    
			continue;
1995/0725    
1997/0327    
		/*
2000/0517/sys/src/9/pc/pci.c:61,66 – 2000/0617/sys/src/9/pc/pci.c:61,67 (short | long)
1997/0327    
static Lock pcicfglock; 
static Lock pcicfginitlock;
1995/0725    
static int pcicfgmode = -1;
2000/0617    
static int pcimaxbno = 255;
1997/0327    
static int pcimaxdno; 
static Pcidev* pciroot;
1997/1011    
static Pcidev* pcilist;
2000/0517/sys/src/9/pc/pci.c:534,544 – 2000/0617/sys/src/9/pc/pci.c:535,547
1999/0301    
1999/0622    
	fmtinstall('T', tbdfconv);
2000/0617    
	if(p = getconf("*pcimaxbno")) 
		pcimaxbno = strtoul(p, 0, 0);
1999/0301    
	if(p = getconf("*pcimaxdno")) 
		pcimaxdno = strtoul(p, 0, 0); 
 
	list = &pciroot; 
	for(bno = 0; bno < 256; bno++) {
2000/0617    
	for(bno = 0; bno <= pcimaxbno; bno++) {
1999/0301    
		bno = pciscan(bno, list); 
		while(*list) 
			list = &(*list)->link;
Too many diffs (26 > 25). Stopping.


source code copyright © 1990-2005 Lucent Technologies; see license
Plan 9 distribution
comments to russ cox (rsc@swtch.com)