plan 9 kernel history: overview | file list | diff list

2000/0515/alphapc/arch164.c (diff list | history)

1999/0415/sys/src/9/alphapc/arch164.c:54,62 – 1999/0423/sys/src/9/alphapc/arch164.c:54,63 (short | long)
1999/0415    
	} 
	coresave[0] = core[0x140/4]; 
 
	/* direct map bottom 2G PCI target space to KZERO in window 1 */ 
	wind[0x500/4] = KZERO|1; 
	wind[0x540/4] = 0x7ff00000;
1999/0423    
#ifdef notdef 
	/* direct map bottom 1G PCI target space to KZERO in window 1 */ 
	wind[0x500/4] = PCIWINDOW|1; 
	wind[0x540/4] = 0x3ff00000;
1999/0415    
	wind[0x580/4] = 0; 
 
	/* disable other windows */
1999/0415/sys/src/9/alphapc/arch164.c:63,68 – 1999/0423/sys/src/9/alphapc/arch164.c:64,70
1999/0415    
	wind[0x400/4] = 0; 
	wind[0x600/4] = 0; 
	wind[0x700/4] = 0;
1999/0423    
#endif /* notdef */
1999/0415    
 
	/* clear error state */ 
	core[0x8200/4] = 0x7ff;
1999/0415/sys/src/9/alphapc/arch164.c:263,268 – 1999/0423/sys/src/9/alphapc/arch164.c:265,271
1999/0415    
{ 
	mb(); 
	*(uchar*)(iobase(port)) = val;
1999/0423    
	mb();
1999/0415    
} 
 
void
1999/0415/sys/src/9/alphapc/arch164.c:270,275 – 1999/0423/sys/src/9/alphapc/arch164.c:273,279
1999/0415    
{ 
	mb(); 
	*(ushort*)(iobase(port)) = val;
1999/0423    
	mb();
1999/0415    
} 
 
void
1999/0415/sys/src/9/alphapc/arch164.c:277,282 – 1999/0423/sys/src/9/alphapc/arch164.c:281,287
1999/0415    
{ 
	mb(); 
	*(ulong*)(iobase(port)) = val;
1999/0423    
	mb();
1999/0415    
} 
 
void
1999/0423/sys/src/9/alphapc/arch164.c:27,32 – 1999/0424/sys/src/9/alphapc/arch164.c:27,52 (short | long)
1999/0415    
	return 0;	/* bug! */ 
}
1999/0424    
static uvlong* sgmap; 
 
static void 
sginit(void) 
{ 
	ulong pa; 
	uvlong *pte; 
 
	sgmap = xspanalloc(BY2PG, BY2PG, 0); 
	memset(sgmap, 0, BY2PG); 
 
	pte = sgmap; 
	for(pa = 0; pa < 8*1024*1024; pa += BY2PG) 
		*pte++ = ((pa>>PGSHIFT)<<1)|1; 
 
	wind[0x400/4] = ISAWINDOW|2; 
	wind[0x440/4] = 0x00700000; 
	wind[0x480/4] = PADDR(sgmap); 
}
1999/0415    
static void * 
kmapio(ulong space, ulong offset, int size) 
{
1999/0423/sys/src/9/alphapc/arch164.c:54,70 – 1999/0424/sys/src/9/alphapc/arch164.c:74,91
1999/0415    
	} 
	coresave[0] = core[0x140/4];
1999/0423    
#ifdef notdef
1999/0424    
	/* disable windows */ 
	wind[0x400/4] = 0; 
	wind[0x500/4] = 0; 
	wind[0x600/4] = 0; 
	wind[0x700/4] = 0;
1999/0423    
	/* direct map bottom 1G PCI target space to KZERO in window 1 */ 
	wind[0x500/4] = PCIWINDOW|1; 
	wind[0x540/4] = 0x3ff00000;
1999/0415    
	wind[0x580/4] = 0; 
 
	/* disable other windows */ 
	wind[0x400/4] = 0; 
	wind[0x600/4] = 0; 
	wind[0x700/4] = 0;
1999/0423    
#endif /* notdef */
1999/0424    
sginit();
1999/0415    
 
	/* clear error state */ 
	core[0x8200/4] = 0x7ff;
1999/0424/sys/src/9/alphapc/arch164.c:42,48 – 1999/0501/sys/src/9/alphapc/arch164.c:42,48 (short | long)
1999/0424    
	for(pa = 0; pa < 8*1024*1024; pa += BY2PG) 
		*pte++ = ((pa>>PGSHIFT)<<1)|1; 
 
	wind[0x400/4] = ISAWINDOW|2;
1999/0501    
	wind[0x400/4] = ISAWINDOW|4|2|1;
1999/0424    
	wind[0x440/4] = 0x00700000; 
	wind[0x480/4] = PADDR(sgmap); 
}
1999/0424/sys/src/9/alphapc/arch164.c:91,97 – 1999/0501/sys/src/9/alphapc/arch164.c:91,97
1999/0415    
	core[0x8200/4] = 0x7ff; 
 
	/* set config: byte/word enable, no monster window, etc. */ 
	core[0x140/4] = 1;
1999/0501    
	core[0x140/4] = 0x21;
1999/0415    
 
	/* turn off mcheck on master abort.  now we can probe PCI space. */ 
	core[0x8280/4] &= ~(1<<7);
1999/0424/sys/src/9/alphapc/arch164.c:99,104 – 1999/0501/sys/src/9/alphapc/arch164.c:99,110
1999/0415    
	/* set up interrupts. */ 
	i8259init(); 
	cserve(52, 4);		/* enable SIO interrupt */
1999/0501    
} 
 
void 
ciaerror(void) 
{ 
	print("cia error 0x%luX\n", core[0x8200/4]);
1999/0415    
} 
 
static void
1999/0501/sys/src/9/alphapc/arch164.c:42,50 – 1999/0507/sys/src/9/alphapc/arch164.c:42,52 (short | long)
1999/0424    
	for(pa = 0; pa < 8*1024*1024; pa += BY2PG) 
		*pte++ = ((pa>>PGSHIFT)<<1)|1;
1999/0501    
	wind[0x400/4] = ISAWINDOW|4|2|1;
1999/0507    
	wind[0x400/4] = ISAWINDOW|2|1;
1999/0424    
	wind[0x440/4] = 0x00700000; 
	wind[0x480/4] = PADDR(sgmap);
1999/0507    
	wind[0x480/4] = PADDR(sgmap)>>2; 
 
	wind[0x100/4] = 3;	/* invalidate tlb cache */
1999/0424    
}
1999/0415    
static void *
1999/0501/sys/src/9/alphapc/arch164.c:110,116 – 1999/0507/sys/src/9/alphapc/arch164.c:112,118
1999/0415    
static void 
corehello(void) 
{ 
	print("cpu%d: CIA revision %d; cnfg %lux cntrl %lux\n",
1999/0507    
	print("cpu%d: CIA revision %ld; cnfg %lux cntrl %lux\n",
1999/0415    
			0,	/* BUG */ 
			core[0x80/4] & 0x7f, core[0x140/4], core[0x100/4]); 
	print("cpu%d: HAE_IO %lux\n", 0, core[0x440/4]);
1999/0507/sys/src/9/alphapc/arch164.c:44,52 – 1999/0511/sys/src/9/alphapc/arch164.c:44,52 (short | long)
1999/0424    
1999/0507    
	wind[0x400/4] = ISAWINDOW|2|1;
1999/0424    
	wind[0x440/4] = 0x00700000;
1999/0507    
	wind[0x480/4] = PADDR(sgmap)>>2;
1999/0511    
	wind[0x480/4] = PADDR(sgmap)>>2;	/* why the shift? */
1999/0507    
 
	wind[0x100/4] = 3;	/* invalidate tlb cache */
1999/0511    
	wind[0x100/4] = 3;			/* invalidate tlb cache */
1999/0424    
}
1999/0415    
static void *
1999/0511/sys/src/9/alphapc/arch164.c:164,263 – 2000/0401/sys/src/9/alphapc/arch164.c:164,189 (short | long)
1999/0415    
	return kmapio(0x88, addr, len); 
} 
 
/* 
 *	interrupts -- adapted from PC, needs work. 
 */ 
                 
static Lock irqctllock; 
static Irqctl *irqctl[256]; 
static char irqmask[3]; 
                 
static void 
intr164(Ureg *ur)
2000/0401    
static int 
intrenable164(Vctl *v)
1999/0415    
{ 
	int i, v; 
	Irqctl *ctl; 
	Irq *irq; 
	Mach *mach;
2000/0401    
	int vec, irq;
1999/0415    
 
	v = (ulong)ur->a1>>4; 
	if (v < 0x80) { 
		iprint("unknown device intr v %d\n", v); 
		return;
2000/0401    
	irq = v->irq; 
	if(irq > MaxIrqPIC) { 
		print("intrenable: irq %d out of range\n", v->irq); 
		return -1;
1999/0415    
	} 
	v -= 0x80; 
	if(v < 256 && (ctl = irqctl[v])){ 
		if(ctl->isintr){ 
			m->intr++; 
			if(ctl->isr) 
				ctl->isr(v); 
/*				if(v >= VectorPIC && v <= MaxVectorPIC) 
				m->lastintr = v-VectorPIC; */ 
		} 
                 
		for(irq = ctl->irq; irq; irq = irq->next) 
			irq->f(ur, irq->a); 
                 
		if(ctl->eoi) 
			ctl->eoi(v);
2000/0401    
	if(BUSTYPE(v->tbdf) == BusPCI) { 
		vec = irq+VectorPCI; 
		cserve(52, irq);
1999/0415    
	} 
	else if(v >= VectorPIC && v <= MaxVectorPIC){ 
		/* 
		 * An unknown interrupt. 
		 * Check for a default IRQ7. This can happen when 
		 * the IRQ input goes away before the acknowledge. 
		 * In this case, a 'default IRQ7' is generated, but 
		 * the corresponding bit in the ISR isn't set. 
		 * In fact, just ignore all such interrupts. 
		 */ 
		iprint("cpu%d: spurious interrupt %d, last %d", 
			m->machno, v-VectorPIC, 0 /*m->lastintr*/); 
		for(i = 0; i < 32; i++){ 
			if(!(active.machs & (1<<i))) 
				continue; 
			mach = MACHP(i); 
			if(m->machno == mach->machno) 
				continue; 
			iprint(": cpu%d: last %d", mach->machno, 0 /*mach->lastintr*/); 
		} 
		iprint("\n"); 
/*			m->spuriousintr++; */ 
		return; 
	} 
	else{ 
		dumpregs(ur); 
		panic("unknown intr: %d\n", v); /* */ 
	} 
} 
                 
static int 
intrenable164(int v, void (*f)(Ureg*, void*), void*a, int tbdf) 
{ 
	Irq * irq; 
	Irqctl *ctl; 
                 
	lock(&irqctllock); 
	if(irqctl[v] == 0){ 
		ctl = xalloc(sizeof(Irqctl)); 
/* this is all wrong; FIXME! */ 
		if(BUSTYPE(tbdf) == BusPCI) 
			cserve(52, v-VectorPCI); 
		else if(v >= VectorPIC && i8259enable(v, tbdf, ctl) == -1){ 
			unlock(&irqctllock); 
			iprint("intrenable: didn't find v %d, tbdf 0x%uX\n", v, tbdf); 
			xfree(ctl);
2000/0401    
	else { 
		vec = irq+VectorPIC; 
		if(i8259enable(irq, v->tbdf, v) == -1)
1999/0415    
			return -1; 
		} 
		irqctl[v] = ctl; 
	} 
	ctl = irqctl[v]; 
	irq = xalloc(sizeof(Irq)); 
	irq->f = f; 
	irq->a = a; 
	irq->next = ctl->irq; 
	ctl->irq = irq; 
	unlock(&irqctllock); 
	return 0;
2000/0401    
	return vec;
1999/0415    
} 
 
/*
1999/0511/sys/src/9/alphapc/arch164.c:405,411 – 2000/0401/sys/src/9/alphapc/arch164.c:331,336
1999/0415    
	coredetach, 
	pcicfg2117x, 
	pcimem2117x, 
	intr164, 
	intrenable164, 
 
	inb2117x,
2000/0401/sys/src/9/alphapc/arch164.c:38,50 – 2000/0515/sys/src/9/alphapc/arch164.c:38,59 (short | long)
1999/0424    
	sgmap = xspanalloc(BY2PG, BY2PG, 0); 
	memset(sgmap, 0, BY2PG);
2000/0515    
	/* 
	 * Prepare scatter-gather map for 0-8MB. 
	 */
1999/0424    
	pte = sgmap; 
	for(pa = 0; pa < 8*1024*1024; pa += BY2PG) 
		*pte++ = ((pa>>PGSHIFT)<<1)|1;
1999/0507    
	wind[0x400/4] = ISAWINDOW|2|1;
1999/0424    
	wind[0x440/4] = 0x00700000;
1999/0511    
	wind[0x480/4] = PADDR(sgmap)>>2;	/* why the shift? */
2000/0515    
	/* 
	 * Set up a map for ISA DMA accesses to physical memory. 
	 * Addresses presented by an ISA device between ISAWINDOW 
	 * and ISAWINDOW+8MB will be translated to between 0 and 
	 * 0+8MB of physical memory. 
	 */ 
	wind[0x400/4] = ISAWINDOW|2|1;		/* window base */ 
	wind[0x440/4] = 0x00700000;		/* window mask */ 
	wind[0x480/4] = PADDR(sgmap)>>2;	/* <33:10> of sg map */
1999/0507    
1999/0511    
	wind[0x100/4] = 3;			/* invalidate tlb cache */
1999/0424    
}
2000/0401/sys/src/9/alphapc/arch164.c:82,93 – 2000/0515/sys/src/9/alphapc/arch164.c:91,107
1999/0424    
	wind[0x600/4] = 0; 
	wind[0x700/4] = 0;
1999/0423    
	/* direct map bottom 1G PCI target space to KZERO in window 1 */
2000/0515    
	sginit(); 
 
	/* 
	 * Set up a map for PCI DMA accesses to physical memory. 
	 * Addresses presented by a PCI device between PCIWINDOW 
	 * and PCIWINDOW+1GB will be translated to between 0 and 
	 * 0+1GB of physical memory. 
	 */
1999/0423    
	wind[0x500/4] = PCIWINDOW|1; 
	wind[0x540/4] = 0x3ff00000;
1999/0415    
	wind[0x580/4] = 0; 
                 
1999/0424    
sginit();
1999/0415    
 
	/* clear error state */ 
	core[0x8200/4] = 0x7ff;
2000/0515/sys/src/9/alphapc/arch164.c:346,351 – 2001/1023/sys/src/9/alphapc/arch164.c:346,353 (short | long)
1999/0415    
	pcicfg2117x, 
	pcimem2117x, 
	intrenable164,
2001/1023    
	nil, 
	nil,
1999/0415    
 
	inb2117x, 
	ins2117x,


source code copyright © 1990-2005 Lucent Technologies; see license
Plan 9 distribution
comments to russ cox (rsc@swtch.com)