plan 9 kernel history: overview | file list | diff list

2001/0822/bitsy/l.s (diff list | history)

2000/0831/sys/src/9/bitsy/l.s:1,116 – 2000/0901/sys/src/9/bitsy/l.s:1,84 (short | long)
2000/0831    
#include "mem.h" 
#include "arm7500.h"
2000/0901    
#include "sa1110.h"
2000/0831    
#include "io.h" 
 
/* 
 * Entered here from the boot loader with 
 *	MMU, IDC and WB enabled.
2000/0901    
 * Entered here from Compaq's bootldr with MMU disabled.
2000/0831    
 */ 
TEXT _startup(SB), $-4 
	MOVW	$setR12(SB), R12
2000/0901    
TEXT _start(SB), $-4 
	MOVW	$setR12(SB), R12		/* load the SB */
2000/0831    
_main: 
	MOVW	$(PsrDirq|PsrDfiq|PsrMsvc), R1	/* SVC mode, interrupts disabled */
2000/0901    
	/* SVC mode, interrupts disabled */ 
	MOVW	$(PsrDirq|PsrDfiq|PsrMsvc), R1
2000/0831    
	MOVW	R1, CPSR
2000/0901    
 
	/* turn on caches and write buffer */ 
	MRC	CpMMU, 0, R1, C(CpControl), C(0x0) 
	ORR	$(CpCdcache|CpCwb), R1 
	MCR     CpMMU, 0, R1, C(CpControl), C(0x0)
2000/0831    
	MOVW	$(MACHADDR+BY2PG), R13		/* stack */ 
	SUB	$4, R13				/* link */ 
	BL	main(SB) 
                 
2000/0901    
	BL	exit(SB) 
	/* we shouldn't get here */
2000/0831    
_mainloop: 
	BEQ	_mainloop 
	BNE	_mainloop 
	BL	_div(SB)			/* loader botch */ 
	BL	_mainloop
2000/0901    
	B	_mainloop
2000/0831    
 
TEXT mmuregr(SB), $-4 
	CMP	$CpCPUID, R0 
	BNE	_fsrr 
	MRC	CpMMU, 0, R0, C(CpCPUID), C(0)
2000/0901    
/* flush tlb's */ 
TEXT flushmmu(SB), $-4 
	MCR	CpMMU, 0, R0, C(CpTLBFlush), C(0x0)
2000/0831    
	RET 
 
_fsrr: 
	CMP	$CpFSR, R0 
	BNE	_farr 
	MRC	CpMMU, 0, R0, C(CpFSR), C(0)
2000/0901    
/* flush instruction cache */ 
TEXT flushicache(SB), $-4 
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0x0) 
	/* drain prefetch */ 
	MOVW	R0,R0					 
	MOVW	R0,R0 
	MOVW	R0,R0 
	MOVW	R0,R0
2000/0831    
	RET 
 
_farr: 
	CMP	$CpFAR, R0 
	BNE	_ctlr 
	MRC	CpMMU, 0, R0, C(CpFAR), C(0)
2000/0901    
/* flush data cache */ 
TEXT flushdcache(SB), $-4 
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0x0)
2000/0831    
	RET 
 
_ctlr: 
	CMP	$CpControl, R0 
	BNE	_mmuregbad 
	MCR	CpMMU, 0, R0, C(CpControl), C(0)
2000/0901    
/* flush i and d caches */ 
TEXT flushcache(SB), $-4 
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0x0) 
	/* drain prefetch */ 
	MOVW	R0,R0						 
	MOVW	R0,R0 
	MOVW	R0,R0 
	MOVW	R0,R0
2000/0831    
	RET 
 
_mmuregbad: 
	MOVW	$-1, R0
2000/0901    
/* drain write buffer */ 
TEXT drainwb(SB), $-4 
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0x0), 4
2000/0831    
	RET 
 
TEXT mmuregw(SB), $-4 
	CMP	$CpControl, R0 
	BNE	_ttbw 
	MOVW	4(FP), R0 
	MCR	CpMMU, 0, R0, C(CpControl), C(0)
2000/0901    
/* return cpu id */ 
TEXT getcpuid(SB), $-4 
	MRC	CpMMU, 0, R0, C(CpControl), C(0x0)
2000/0831    
	RET 
 
_ttbw: 
	CMP	$CpTTB, R0 
	BNE	_dacw 
	MOVW	4(FP), R0 
	MCR	CpMMU, 0, R0, C(CpTTB), C(0)
2000/0901    
/* return fault status */ 
TEXT getfsr(SB), $-4 
	MRC	CpMMU, 0, R0, C(CpFSR), C(0x0)
2000/0831    
	RET 
 
_dacw: 
	CMP	$CpDAC, R0 
	BNE	_TLBflushw 
	MOVW	4(FP), R0 
	MCR	CpMMU, 0, R0, C(CpDAC), C(0)
2000/0901    
/* return fault address */ 
TEXT getfar(SB), $-4 
	MRC	CpMMU, 0, R0, C(CpFAR), C(0x0)
2000/0831    
	RET 
 
_TLBflushw: 
	CMP	$CpTLBflush, R0 
	BNE	_TLBpurgew 
	MCR	CpMMU, 0, R0, C(CpTLBflush), C(0) 
	RET
2000/0901    
/* st the translation table base */ 
TEXT setttb(SB), $-4 
	MCR	CpMMU, 0, R0, C(CpTTB), C(0x0)
2000/0831    
 
_TLBpurgew: 
	CMP	$CpTLBpurge, R0 
	BNE	_IDCflushw 
	MOVW	4(FP), R0 
	MCR	CpMMU, 0, R0, C(CpTLBpurge), C(0) 
	RET 
                 
_IDCflushw: 
	CMP	$CpIDCflush, R0 
	BNE	_WBdrain 
	MCR	CpMMU, 0, R0, C(CpIDCflush), C(CpIDCflush) 
	RET 
                 
_WBdrain: 
	CMP	$CpWBdrain, R0 
	BNE	_mmuregbad 
	MCR	CpMMU, 4, R0, C(CpIDCflush), C(CpWBdrain), 4 
	RET 
                 
TEXT mmuttb(SB), $-4 
	MCR	CpMMU, 0, R0, C(CpIDCflush), C(CpIDCflush) 
	MCR	CpMMU, 0, R0, C(CpTLBflush), C(0) 
	MCR	CpMMU, 0, R0, C(CpTTB), C(0) 
	RET 
                 
TEXT mmureset(SB), $-4 
	MOVW	CPSR, R0 
	ORR	$(PsrDfiq|PsrDirq), R0, R0 
	MOVW	R0, CPSR 
                 
	MOVW	$0, R0 
	MOVW	$(CpCsystem), R1 
	MCR	CpMMU, 0, R1, C(CpControl), C(0) 
	B	(R0) 
                 
TEXT setr13(SB), $-4 
	MOVW	4(FP), R1
2000/0831/sys/src/9/bitsy/l.s:237,249 – 2000/0901/sys/src/9/bitsy/l.s:205,210
2000/0831    
	EOR	$(PsrDfiq|PsrDirq), R0 
	RET 
 
TEXT _exit(SB), $-4 
	MRC	CpMMU, 0, R1, C(CpControl), C(0), 0	/* Read MMUCR */ 
	BIC	$MMUCR_M_ENABLE, R1			/* Clear MMU Enable bit */ 
	MCR	CpMMU, 0, R1, C(CpControl), C(0), 0	/* Write to MMU CR */ 
	MCR	CpMMU, 0, R1, C(CpIDCflush), C(7)	/* Flush (inval) I,D-cache */ 
	B	(R0) 
                 
TEXT cpsrr(SB), $-4 
	MOVW	CPSR, R0 
	RET
2000/0831/sys/src/9/bitsy/l.s:293,354 – 2000/0901/sys/src/9/bitsy/l.s:254,256
2000/0831    
	MOVW		R0, R0 
	MOVW		R0, R0 
	RET	 
                 
TEXT flushIcache(SB), $-4 
	MCR	 	CpMMU, 0, R0, C(CpCacheCtl), C(5), 0	 
	MOVW		R0,R0							 
	MOVW		R0,R0 
	MOVW		R0,R0 
	MOVW		R0,R0 
	RET 
                 
TEXT cleanDentry(SB), $-4 
	MCR		CpMMU, 0, R0, C(CpCacheCtl), C(10), 1 
	RET 
                 
TEXT flushDentry(SB), $-4 
	MCR		CpMMU, 0, R0, C(CpCacheCtl), C(6), 1 
	RET 
                 
TEXT drainWBuffer(SB), $-4 
	MCR		CpMMU, 0, R0, C(CpCacheCtl), C(10), 4	 
	RET 
                 
TEXT writeBackDC(SB), $-4 
	MOVW		$0xE0000000, R0 
	MOVW		$8192, R1 
	ADD		R0, R1 
                 
wbflush: 
	MOVW.P.W	32(R0), R2 
	CMP		R1,R0 
	BNE		wbflush 
	RET 
                 
TEXT flushDcache(SB), $-4 
	MCR		CpMMU, 0, R0, C(CpCacheCtl), C(6), 0	 
	RET 
                 
TEXT writeBackBDC(SB), $-4		 
	MOVW		$0xE4000000, R0 
	MOVW		$0x200, R1 
	ADD		R0, R1 
                 
wbbflush: 
	MOVW.P.W	32(R0), R2 
	CMP		R1,R0 
	BNE		wbbflush 
	MCR		CpMMU, 0, R0, C(CpCacheCtl), C(10), 4	 
	MOVW		R0,R0								 
	MOVW		R0,R0 
	MOVW		R0,R0 
	MOVW		R0,R0 
	RET 
                 
TEXT flushIDC(SB), $-4 
/*BUG*/ 
	BL 		drainWBuffer(SB) 
	BL 		writeBackDC(SB) 
	BL 		flushDcache(SB)  
	BL 		flushIcache(SB)	 
	RET
2000/0901/sys/src/9/bitsy/l.s:17,27 – 2000/0902/sys/src/9/bitsy/l.s:17,31 (short | long)
2000/0901    
	ORR	$(CpCdcache|CpCwb), R1 
	MCR     CpMMU, 0, R1, C(CpControl), C(0x0)
2000/0902    
	/* turn off interrupts */ 
	BL	splhi(SB)
2000/0831    
	MOVW	$(MACHADDR+BY2PG), R13		/* stack */ 
	SUB	$4, R13				/* link */ 
	BL	main(SB)
2000/0901    
	BL	exit(SB) 
	/* we shouldn't get here */
2000/0902    
	BL	_div(SB)			/* hack to get _div etc loaded */
2000/0831    
_mainloop:
2000/0901    
	B	_mainloop
2000/0831    
2000/0901/sys/src/9/bitsy/l.s:162,173 – 2000/0902/sys/src/9/bitsy/l.s:166,178
2000/0831    
	MOVM.IA	  (R3), [R0-R3]		/* restore [R0-R3] */ 
	B	_vsaveu
2000/0902    
	/* push the registers as in ureg */
2000/0831    
_vsaveu: 
	SUB	$4, R13			/* save link */ 
	MOVW	R14, (R13) 
	MOVM.DB.W [R0-R14], (R13)	/* save svc registers */
2000/0902    
	MOVM.DB.W.S [R0-R14], (R13)	/* save svc registers */
2000/0831    
 
	MOVW	$setR12(SB), R12	/* safety */
2000/0902    
	MOVW	$setR12(SB), R12	/* the SB from user mode is different */
2000/0831    
	MOVW	R13, R0			/* argument is &ureg */ 
	SUB	$8, R13			/* space for argument+link */ 
	BL	exception(SB)
2000/0901/sys/src/9/bitsy/l.s:177,183 – 2000/0902/sys/src/9/bitsy/l.s:182,188
2000/0831    
	MOVW	(R13), R14		/* restore link */ 
	MOVW	8(R13), R0		/* restore SPSR */ 
	MOVW	R0, SPSR 
	MOVM.DB (R13), [R0-R14]	/* restore registers */
2000/0902    
	MOVM.DB.S (R13), [R0-R14]		/* restore registers */
2000/0831    
	ADD	$12, R13		/* skip saved link+type+SPSR */ 
	RFE				/* MOVM.IA.S.W (R13), [R15] */
2000/0901/sys/src/9/bitsy/l.s:194,199 – 2000/0902/sys/src/9/bitsy/l.s:199,210
2000/0831    
	RET 
 
TEXT splx(SB), $-4
2000/0902    
	MOVW	R0, R1 
	MOVW	CPSR, R0 
	MOVW	R1, CPSR 
	RET 
 
TEXT splxpc(SB), $0				/* for iunlock */
2000/0831    
	MOVW	R0, R1 
	MOVW	CPSR, R0 
	MOVW	R1, CPSR
2000/0902/sys/src/9/bitsy/l.s:123,189 – 2000/0903/sys/src/9/bitsy/l.s:123,193 (short | long)
2000/0831    
	B	_vswitch 
 
TEXT _vsvc(SB), $-4				/* reset or SWI or reserved */ 
	SUB	$12, R13 
	MOVW	R14, 8(R13) 
	MOVW	CPSR, R14 
	MOVW	R14, 4(R13) 
	MOVW	$PsrMsvc, R14 
	MOVW	R14, (R13) 
	MOVW	8(R13), R14
2000/0903    
	SUB	$12, R13			/* make room for pc, psr, & type */ 
	MOVW	R14, 8(R13)			/* ureg->pc = interupted PC */ 
	MOVW	SPSR, R14			/* ureg->psr = SPSR */ 
	MOVW	R14, 4(R13)			/* ... */ 
	MOVW	$PsrMsvc, R14			/* ureg->type = PsrMsvc */ 
	MOVW	R14, (R13)			/* ... */
2000/0831    
	B	_vsaveu 
 
TEXT _vpab(SB), $-4				/* prefetch abort */ 
	MOVM.IA	[R0-R3], (R13) 
	MOVW	$PsrMabt, R0
2000/0903    
	MOVM.IA	[R0-R3], (R13)			/* free some working space */ 
	MOVW	$PsrMabt, R0			/* r0 = type */
2000/0831    
	B	_vswitch 
 
TEXT _vdab(SB), $-4				/* data abort */ 
	MOVM.IA	[R0-R3], (R13) 
	MOVW	$(PsrMabt+1), R0 
	B	_vswitch
2000/0903    
	MOVM.IA	[R0-R3], (R13)			/* free some working space */ 
	MOVW	$(PsrMabt+1), R0		/* r0 = type */ 
	B	_vswitch			/*
2000/0831    
 
TEXT _virq(SB), $-4				/* IRQ */ 
	MOVM.IA	[R0-R3], (R13) 
	MOVW	$PsrMirq, R0
2000/0903    
	MOVM.IA	[R0-R3], (R13)			/* free some working space */ 
	MOVW	$PsrMirq, R0			/* r0 = type */
2000/0831    
	B	_vswitch 
 
TEXT _vfiq(SB), $-4				/* FIQ */ 
	MOVM.IA	[R0-R3], (R13) 
	MOVW	$PsrMfiq, R0
2000/0903    
	MOVM.IA	[R0-R3], (R13)			/* free some working space */ 
	MOVW	$PsrMfiq, R0			/* r0 = type */
2000/0831    
	B	_vswitch
2000/0903    
	/* 
	 *  come here with type in R0 and R13 pointing above saved [r0-r3] 
	 */
2000/0831    
_vswitch:				/* switch to svc, type in R0 */ 
	MOVW	SPSR, R1		/* psr for ureg */ 
	MOVW	R14, R2			/* saved pc for ureg */
2000/0903    
	MOVW	SPSR, R1		/* SPSR for ureg */ 
	MOVW	R14, R2			/* interrupted pc for ureg */
2000/0831    
	MOVW	R13, R3			/* [R0-R3] save area */ 
 
	MOVW	CPSR, R14		/* switch */
2000/0903    
	/* switch to svc mode, we get new R13 pointing to top of svc stack */ 
	MOVW	CPSR, R14
2000/0831    
	BIC	$PsrMask, R14 
	ORR	$(PsrDirq|PsrDfiq|PsrMsvc), R14 
	MOVW	R14, CPSR 
 
	MOVM.DB.W [R0-R2], (R13)	/* top of ureg */ 
	MOVM.IA	  (R3), [R0-R3]		/* restore [R0-R3] */
2000/0903    
	MOVM.DB.W [R0-R2], (R13)	/* set ureg->{pc, psr, type}; r13 points to ureg->type  */ 
	MOVM.IA	  (R3), [R0-R3]		/* restore [R0-R3] from previous mode's stack */
2000/0831    
	B	_vsaveu
2000/0902    
	/* push the registers as in ureg */
2000/0903    
	/*  
	 *  come here with R13 pointing to ureg->type 
	 */
2000/0831    
_vsaveu: 
	SUB	$4, R13			/* save link */ 
	MOVW	R14, (R13)
2000/0902    
	MOVM.DB.W.S [R0-R14], (R13)	/* save svc registers */
2000/0903    
	MOVM.DB.W.S [R0-R14], (R13)	/* save user level registers, r13 points to ureg */
2000/0831    
2000/0902    
	MOVW	$setR12(SB), R12	/* the SB from user mode is different */
2000/0831    
	MOVW	R13, R0			/* argument is &ureg */
2000/0903    
 
	MOVW	R13, R0			/* first arg is pointer to ureg */
2000/0831    
	SUB	$8, R13			/* space for argument+link */ 
	BL	exception(SB) 
 
_vrfe: 
	ADD	$(8+4*15), R13		/* [r0-R14]+argument+link */ 
	MOVW	(R13), R14		/* restore link */ 
	MOVW	8(R13), R0		/* restore SPSR */ 
	MOVW	R0, SPSR
2000/0902    
	MOVM.DB.S (R13), [R0-R14]		/* restore registers */
2000/0831    
	ADD	$12, R13		/* skip saved link+type+SPSR */
2000/0903    
_vrfe:  
	ADD	$(8+4*15), R13		/* r13 points to ureg->type */ 
	MOVW	8(R13), R14		/* restore link */ 
	MOVW	4(R13), R0		/* restore SPSR */ 
	MOVW	R0, SPSR		/* ... */ 
	MOVM.DB.S (R13), [R0-R14]	/* restore registers */ 
	ADD	$8, R13			/* skip saved type+SPSR */
2000/0831    
	RFE				/* MOVM.IA.S.W (R13), [R15] */ 
 
TEXT splhi(SB), $-4
2000/0903/sys/src/9/bitsy/l.s:25,33 – 2000/0904/sys/src/9/bitsy/l.s:25,33 (short | long)
2000/0831    
	BL	main(SB)
2000/0901    
	BL	exit(SB) 
	/* we shouldn't get here */
2000/0902    
	BL	_div(SB)			/* hack to get _div etc loaded */
2000/0831    
_mainloop:
2000/0901    
	B	_mainloop
2000/0904    
	BL	_div(SB)			/* hack to get _div etc loaded */
2000/0831    
2000/0901    
/* flush tlb's */ 
TEXT flushmmu(SB), $-4
2000/0903/sys/src/9/bitsy/l.s:79,88 – 2000/0904/sys/src/9/bitsy/l.s:79,91
2000/0901    
	MRC	CpMMU, 0, R0, C(CpFAR), C(0x0)
2000/0831    
	RET
2000/0901    
/* st the translation table base */
2000/0904    
/* set the translation table base */
2000/0901    
TEXT setttb(SB), $-4 
	MCR	CpMMU, 0, R0, C(CpTTB), C(0x0)
2000/0831    
2000/0904    
/* 
 *  set the stack value for the mode passed in R0 
 */
2000/0831    
TEXT setr13(SB), $-4 
	MOVW	4(FP), R1
2000/0903/sys/src/9/bitsy/l.s:97,193 – 2000/0904/sys/src/9/bitsy/l.s:100,207
2000/0831    
	MOVW	R2, CPSR 
	RET
2000/0904    
/* 
 *  exception vectors, copied by trapinit() to somewhere useful 
 */
2000/0831    
TEXT vectors(SB), $-4 
	MOVW	0x18(R15), R15			/* reset */ 
	MOVW	0x18(R15), R15			/* undefined */ 
	MOVW	0x18(R15), R15			/* SWI */ 
	MOVW	0x18(R15), R15			/* prefetch abort */ 
	MOVW	0x18(R15), R15			/* data abort */ 
	MOVW	0x18(R15), R15			/* reserved */ 
	MOVW	0x18(R15), R15			/* IRQ */ 
	MOVW	0x18(R15), R15			/* FIQ */
2000/0904    
	MOVW	0x18(R15), R15		/* reset */ 
	MOVW	0x18(R15), R15		/* undefined */ 
	MOVW	0x18(R15), R15		/* SWI */ 
	MOVW	0x18(R15), R15		/* prefetch abort */ 
	MOVW	0x18(R15), R15		/* data abort */ 
	MOVW	0x18(R15), R15		/* reserved */ 
	MOVW	0x18(R15), R15		/* IRQ */ 
	MOVW	0x18(R15), R15		/* FIQ */ 
	WORD	$_vsvc(SB)		/* reset, in svc mode already */ 
	WORD	$_vund(SB)		/* undefined, switch to svc mode */ 
	WORD	$_vsvc(SB)		/* swi, in svc mode already */ 
	WORD	$_vpab(SB)		/* prefetch abort, switch to svc mode */ 
	WORD	$_vdab(SB)		/* data abort, switch to svc mode */ 
	WORD	$_vsvc(SB)		/* reserved */ 
	WORD	$_virq(SB)		/* IRQ, switch to svc mode */ 
	WORD	$_vfiq(SB)		/* FIQ, switch to svc mode */
2000/0831    
 
TEXT vtable(SB), $-4 
	WORD	$_vsvc(SB)			/* reset, in svc mode already */ 
	WORD	$_vund(SB)			/* undefined, switch to svc mode */ 
	WORD	$_vsvc(SB)			/* swi, in svc mode already */ 
	WORD	$_vpab(SB)			/* prefetch abort, switch to svc mode */ 
	WORD	$_vdab(SB)			/* data abort, switch to svc mode */ 
	WORD	$_vsvc(SB)			/* reserved */ 
	WORD	$_virq(SB)			/* IRQ, switch to svc mode */ 
	WORD	$_vfiq(SB)			/* FIQ, switch to svc mode */
2000/0904    
TEXT _vsvc(SB), $-4			/* reset or SWI or reserved */ 
	SUB	$12, R13		/* make room for pc, psr, & type */ 
	MOVW	R14, 8(R13)		/* ureg->pc = interupted PC */ 
	MOVW	SPSR, R14		/* ureg->psr = SPSR */ 
	MOVW	R14, 4(R13)		/* ... */ 
	MOVW	$PsrMsvc, R14		/* ureg->type = PsrMsvc */ 
	MOVW	R14, (R13)		/* ... */ 
	MOVM.DB.W.S [R0-R14], (R13)	/* save user level registers, at end r13 points to ureg */ 
	B	_vexcep			/* call the exception handler */
2000/0831    
 
TEXT _vund(SB), $-4				/* undefined */ 
	MOVM.IA	[R0-R3], (R13)
2000/0904    
TEXT _vund(SB), $-4			/* undefined */ 
	MOVM.IA	[R0-R3], (R13)		/* free some working space */
2000/0831    
	MOVW	$PsrMund, R0 
	B	_vswitch 
 
TEXT _vsvc(SB), $-4				/* reset or SWI or reserved */
2000/0903    
	SUB	$12, R13			/* make room for pc, psr, & type */ 
	MOVW	R14, 8(R13)			/* ureg->pc = interupted PC */ 
	MOVW	SPSR, R14			/* ureg->psr = SPSR */ 
	MOVW	R14, 4(R13)			/* ... */ 
	MOVW	$PsrMsvc, R14			/* ureg->type = PsrMsvc */ 
	MOVW	R14, (R13)			/* ... */
2000/0831    
	B	_vsaveu 
                 
TEXT _vpab(SB), $-4				/* prefetch abort */
2000/0903    
	MOVM.IA	[R0-R3], (R13)			/* free some working space */ 
	MOVW	$PsrMabt, R0			/* r0 = type */
2000/0904    
TEXT _vpab(SB), $-4			/* prefetch abort */ 
	MOVM.IA	[R0-R3], (R13)		/* free some working space */ 
	MOVW	$PsrMabt, R0		/* r0 = type */
2000/0831    
	B	_vswitch 
 
TEXT _vdab(SB), $-4				/* data abort */
2000/0903    
	MOVM.IA	[R0-R3], (R13)			/* free some working space */ 
	MOVW	$(PsrMabt+1), R0		/* r0 = type */ 
	B	_vswitch			/*
2000/0831    
                 
TEXT _virq(SB), $-4				/* IRQ */
2000/0903    
	MOVM.IA	[R0-R3], (R13)			/* free some working space */ 
	MOVW	$PsrMirq, R0			/* r0 = type */
2000/0904    
TEXT _vdab(SB), $-4			/* data abort */ 
	MOVM.IA	[R0-R3], (R13)		/* free some working space */ 
	MOVW	$(PsrMabt+1), R0	/* r0 = type */
2000/0831    
	B	_vswitch 
 
TEXT _vfiq(SB), $-4				/* FIQ */
2000/0903    
	MOVM.IA	[R0-R3], (R13)			/* free some working space */ 
	MOVW	$PsrMfiq, R0			/* r0 = type */
2000/0904    
TEXT _virq(SB), $-4			/* IRQ */ 
	MOVM.IA	[R0-R3], (R13)		/* free some working space */ 
	MOVW	$PsrMirq, R0		/* r0 = type */
2000/0831    
	B	_vswitch
2000/0904    
TEXT _vfiq(SB), $-4			/* FIQ */ 
	RFE				/* RIQ is special, ignore it for now */
2000/0903    
	/* 
	 *  come here with type in R0 and R13 pointing above saved [r0-r3] 
	 */
2000/0831    
_vswitch:				/* switch to svc, type in R0 */
2000/0903    
	MOVW	SPSR, R1		/* SPSR for ureg */ 
	MOVW	R14, R2			/* interrupted pc for ureg */
2000/0831    
	MOVW	R13, R3			/* [R0-R3] save area */
2000/0904    
	MOVW	SPSR, R1		/* save SPSR for ureg */ 
	MOVW	R14, R2			/* save interrupted pc for ureg */ 
	MOVW	R13, R3			/* save pointer to where the original [R0-R3] are */
2000/0831    
2000/0903    
	/* switch to svc mode, we get new R13 pointing to top of svc stack */
2000/0904    
	/* switch to svc mode */
2000/0903    
	MOVW	CPSR, R14
2000/0831    
	BIC	$PsrMask, R14 
	ORR	$(PsrDirq|PsrDfiq|PsrMsvc), R14 
	MOVW	R14, CPSR
2000/0904    
	/* 
	 *  R13 and R14 is now R13_SVC and R14_SVC.  The values of the previous mode's 
	 *  R13 and R14 are no longer accessible.  That's why R3 was left to point to where 
	 *  the old [r0-r3] are stored. 
	 */
2000/0903    
	MOVM.DB.W [R0-R2], (R13)	/* set ureg->{pc, psr, type}; r13 points to ureg->type  */ 
	MOVM.IA	  (R3), [R0-R3]		/* restore [R0-R3] from previous mode's stack */
2000/0831    
	B	_vsaveu
2000/0904    
	MOVM.DB.W.S [R0-R14], (R13)	/* save user level registers, at end r13 points to ureg */
2000/0831    
2000/0903    
	/*  
	 *  come here with R13 pointing to ureg->type
2000/0904    
	/* 
	 *  if the original interrupt happened while executing SVC mode, the User R14 in the Ureg is 
	 *  wrong.  We need to save the SVC one there.
2000/0903    
	 */
2000/0831    
_vsaveu:
2000/0903    
	MOVM.DB.W.S [R0-R14], (R13)	/* save user level registers, r13 points to ureg */
2000/0904    
	MOVW	0x40(R13), R1 
	AND.S	$0xf, R1 
	MOVW.NE	R14,0x38(R13) 
	B	_vexcep
2000/0831    
2000/0902    
	MOVW	$setR12(SB), R12	/* the SB from user mode is different */
2000/0903    
                 
2000/0904    
	/* 
 	 *  call the exception routine, the ureg is at the bottom of the stack 
	 */ 
_vexcep: 
	MOVW	$setR12(SB), R12	/* Make sure we've got the kernel's SB loaded */
2000/0903    
	MOVW	R13, R0			/* first arg is pointer to ureg */
2000/0831    
	SUB	$8, R13			/* space for argument+link */ 
	BL	exception(SB)
2000/0903    
_vrfe:  
	ADD	$(8+4*15), R13		/* r13 points to ureg->type */
2000/0904    
	ADD	$(8+4*15), R13		/* make r13 point to ureg->type */
2000/0903    
	MOVW	8(R13), R14		/* restore link */ 
	MOVW	4(R13), R0		/* restore SPSR */ 
	MOVW	R0, SPSR		/* ... */ 
	MOVM.DB.S (R13), [R0-R14]	/* restore registers */ 
	ADD	$8, R13			/* skip saved type+SPSR */
2000/0904    
	ADD	$8, R13			/* pop past ureg->{type+psr} */
2000/0831    
	RFE				/* MOVM.IA.S.W (R13), [R15] */ 
 
TEXT splhi(SB), $-4
2000/0904/sys/src/9/bitsy/l.s:12,24 – 2000/0905/sys/src/9/bitsy/l.s:12,31 (short | long)
2000/0901    
	MOVW	$(PsrDirq|PsrDfiq|PsrMsvc), R1
2000/0831    
	MOVW	R1, CPSR
2000/0901    
 
	/* turn on caches and write buffer */ 
	MRC	CpMMU, 0, R1, C(CpControl), C(0x0) 
	ORR	$(CpCdcache|CpCwb), R1 
	MCR     CpMMU, 0, R1, C(CpControl), C(0x0)
2000/0905    
	/* flush TLB's */ 
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0x0) 
	/* drain prefetch */ 
	MOVW	R0,R0						 
	MOVW	R0,R0 
	MOVW	R0,R0 
	MOVW	R0,R0
2000/0901    
2000/0902    
	/* turn off interrupts */ 
	BL	splhi(SB)
2000/0905    
	/* drain write buffer */ 
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0x0), 4 
 
	/* disable the MMU */ 
	MOVW	$0x130, R1 
	MCR     CpMMU, 0, R1, C(CpControl), C(0x0)
2000/0902    
2000/0831    
	MOVW	$(MACHADDR+BY2PG), R13		/* stack */ 
	SUB	$4, R13				/* link */
2000/0905/sys/src/9/bitsy/l.s:1,6 – 2000/0906/sys/src/9/bitsy/l.s:1,4 (short | long)
2000/0831    
#include "mem.h"
2000/0901    
#include "sa1110.h"
2000/0831    
#include "io.h" 
 
/*
2000/0901    
 * Entered here from Compaq's bootldr with MMU disabled.
2000/0905/sys/src/9/bitsy/l.s:87,94 – 2000/0906/sys/src/9/bitsy/l.s:85,100
2000/0831    
	RET
2000/0904    
/* set the translation table base */
2000/0901    
TEXT setttb(SB), $-4
2000/0906    
TEXT putttb(SB), $-4
2000/0901    
	MCR	CpMMU, 0, R0, C(CpTTB), C(0x0)
2000/0906    
 
/* set the translation table base */ 
TEXT putdac(SB), $-4 
	MCR	CpMMU, 0, R0, C(CpDAC), C(0x0) 
 
/* set the translation table base */ 
TEXT putpid(SB), $-4 
	MCR	CpMMU, 0, R0, C(CpPID), C(0x0)
2000/0831    
2000/0904    
/* 
 *  set the stack value for the mode passed in R0
2000/0906/sys/src/9/bitsy/l.s:235,241 – 2000/0928/sys/src/9/bitsy/l.s:235,241 (short | long)
2000/0902    
	MOVW	R1, CPSR 
	RET 
 
TEXT splxpc(SB), $0				/* for iunlock */
2000/0928    
TEXT splxpc(SB), $-4				/* for iunlock */
2000/0831    
	MOVW	R0, R1 
	MOVW	CPSR, R0 
	MOVW	R1, CPSR
2000/0928/sys/src/9/bitsy/l.s:65,77 – 2000/0929/sys/src/9/bitsy/l.s:65,77 (short | long)
2000/0831    
	RET
2000/0901    
/* drain write buffer */ 
TEXT drainwb(SB), $-4
2000/0929    
TEXT wbflush(SB), $-4
2000/0901    
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0x0), 4
2000/0831    
	RET
2000/0901    
/* return cpu id */ 
TEXT getcpuid(SB), $-4 
	MRC	CpMMU, 0, R0, C(CpControl), C(0x0)
2000/0929    
	MRC	CpMMU, 0, R0, C(CpCPUID), C(0x0)
2000/0831    
	RET
2000/0901    
/* return fault status */
2000/0928/sys/src/9/bitsy/l.s:87,100 – 2000/0929/sys/src/9/bitsy/l.s:87,118
2000/0904    
/* set the translation table base */
2000/0906    
TEXT putttb(SB), $-4
2000/0901    
	MCR	CpMMU, 0, R0, C(CpTTB), C(0x0)
2000/0929    
	RET
2000/0906    
2000/0929    
/* 
 *  enable mmu, i and d caches, and exception vectors at 0xffff0000 
 */ 
TEXT mmuenable(SB), $-4 
	MRC	CpMMU, 0, R0, C(CpControl), C(0x0) 
	ORR	$(CpCmmuena|CpCdcache|CpCicache|CpCvivec), R0 
	MCR     CpMMU, 0, R0, C(CpControl), C(0x0) 
	RET 
 
TEXT mmudisable(SB), $-4 
	MRC	CpMMU, 0, R0, C(CpControl), C(0x0) 
	BIC	$(CpCmmuena|CpCdcache|CpCicache|CpCvivec), R0 
	MCR     CpMMU, 0, R0, C(CpControl), C(0x0) 
	RET
2000/0906    
/* set the translation table base */ 
TEXT putdac(SB), $-4 
	MCR	CpMMU, 0, R0, C(CpDAC), C(0x0)
2000/0929    
	RET
2000/0906    
 
/* set the translation table base */
2000/0929    
/* set address translation pid */
2000/0906    
TEXT putpid(SB), $-4 
	MCR	CpMMU, 0, R0, C(CpPID), C(0x0)
2000/0929    
	RET
2000/0831    
2000/0904    
/* 
 *  set the stack value for the mode passed in R0
2000/0928/sys/src/9/bitsy/l.s:116,122 – 2000/0929/sys/src/9/bitsy/l.s:134,140
2000/0904    
/* 
 *  exception vectors, copied by trapinit() to somewhere useful 
 */
2000/0831    
TEXT vectors(SB), $-4
2000/0929    
TEXT exceptionvectors(SB), $-4
2000/0904    
	MOVW	0x18(R15), R15		/* reset */ 
	MOVW	0x18(R15), R15		/* undefined */ 
	MOVW	0x18(R15), R15		/* SWI */
2000/0928/sys/src/9/bitsy/l.s:206,212 – 2000/0929/sys/src/9/bitsy/l.s:224,230
2000/0904    
	MOVW	$setR12(SB), R12	/* Make sure we've got the kernel's SB loaded */
2000/0903    
	MOVW	R13, R0			/* first arg is pointer to ureg */
2000/0831    
	SUB	$8, R13			/* space for argument+link */ 
	BL	exception(SB)
2000/0929    
	BL	trap(SB)
2000/0831    
2000/0903    
_vrfe:
2000/0904    
	ADD	$(8+4*15), R13		/* make r13 point to ureg->type */
2000/0929/sys/src/9/bitsy/l.s:143,158 – 2000/1001/sys/src/9/bitsy/l.s:143,161 (short | long)
2000/0904    
	MOVW	0x18(R15), R15		/* reserved */ 
	MOVW	0x18(R15), R15		/* IRQ */ 
	MOVW	0x18(R15), R15		/* FIQ */ 
	WORD	$_vsvc(SB)		/* reset, in svc mode already */
2000/1001    
	WORD	$_vrst(SB)		/* reset, in svc mode already */
2000/0904    
	WORD	$_vund(SB)		/* undefined, switch to svc mode */ 
	WORD	$_vsvc(SB)		/* swi, in svc mode already */ 
	WORD	$_vpab(SB)		/* prefetch abort, switch to svc mode */ 
	WORD	$_vdab(SB)		/* data abort, switch to svc mode */ 
	WORD	$_vsvc(SB)		/* reserved */
2000/1001    
	WORD	$_vabt(SB)		/* prefetch abort, switch to svc mode */ 
	WORD	$_vabt(SB)		/* data abort, switch to svc mode */ 
	WORD	$_vrst(SB)		/* reserved, shouldn't happen */
2000/0904    
	WORD	$_virq(SB)		/* IRQ, switch to svc mode */ 
	WORD	$_vfiq(SB)		/* FIQ, switch to svc mode */
2000/0831    
2000/0904    
TEXT _vsvc(SB), $-4			/* reset or SWI or reserved */
2000/1001    
TEXT _vrst(SB), $-4 
	BL	reset 
 
TEXT _vsvc(SB), $-4			/* SWI */
2000/0904    
	SUB	$12, R13		/* make room for pc, psr, & type */ 
	MOVW	R14, 8(R13)		/* ureg->pc = interupted PC */ 
	MOVW	SPSR, R14		/* ureg->psr = SPSR */
2000/0929/sys/src/9/bitsy/l.s:167,182 – 2000/1001/sys/src/9/bitsy/l.s:170,180
2000/0831    
	MOVW	$PsrMund, R0 
	B	_vswitch
2000/0904    
TEXT _vpab(SB), $-4			/* prefetch abort */
2000/1001    
TEXT _vabt(SB), $-4			/* prefetch abort */
2000/0904    
	MOVM.IA	[R0-R3], (R13)		/* free some working space */ 
	MOVW	$PsrMabt, R0		/* r0 = type */
2000/0831    
	B	_vswitch
2000/0904    
TEXT _vdab(SB), $-4			/* data abort */ 
	MOVM.IA	[R0-R3], (R13)		/* free some working space */ 
	MOVW	$(PsrMabt+1), R0	/* r0 = type */
2000/0831    
	B	_vswitch 
                 
2000/0904    
TEXT _virq(SB), $-4			/* IRQ */ 
	MOVM.IA	[R0-R3], (R13)		/* free some working space */ 
	MOVW	$PsrMirq, R0		/* r0 = type */
2000/0929/sys/src/9/bitsy/l.s:204,216 – 2000/1001/sys/src/9/bitsy/l.s:202,214
2000/0904    
	 *  R13 and R14 are no longer accessible.  That's why R3 was left to point to where 
	 *  the old [r0-r3] are stored. 
	 */
2000/0903    
	MOVM.DB.W [R0-R2], (R13)	/* set ureg->{pc, psr, type}; r13 points to ureg->type  */
2000/1001    
	MOVM.DB.W [R0-R2], (R13)	/* set ureg->{type, psr, pc}; r13 points to ureg->type  */
2000/0903    
	MOVM.IA	  (R3), [R0-R3]		/* restore [R0-R3] from previous mode's stack */
2000/0904    
	MOVM.DB.W.S [R0-R14], (R13)	/* save user level registers, at end r13 points to ureg */
2000/0831    
2000/0904    
	/* 
	 *  if the original interrupt happened while executing SVC mode, the User R14 in the Ureg is 
	 *  wrong.  We need to save the SVC one there.
2000/1001    
	 *  if the original interrupt happened while executing SVC mode, 
	 *  the User R14 in the Ureg is wrong.  We need to save the SVC one there.
2000/0903    
	 */
2000/0904    
	MOVW	0x40(R13), R1 
	AND.S	$0xf, R1
2000/0929/sys/src/9/bitsy/l.s:231,237 – 2000/1001/sys/src/9/bitsy/l.s:229,235
2000/0903    
	MOVW	8(R13), R14		/* restore link */ 
	MOVW	4(R13), R0		/* restore SPSR */ 
	MOVW	R0, SPSR		/* ... */ 
	MOVM.DB.S (R13), [R0-R14]	/* restore registers */
2000/1001    
	MOVM.DB.W.S (R13), [R0-R14]	/* restore registers */
2000/0904    
	ADD	$8, R13			/* pop past ureg->{type+psr} */
2000/0831    
	RFE				/* MOVM.IA.S.W (R13), [R15] */
2000/1001/sys/src/9/bitsy/l.s:153,192 – 2000/1002/sys/src/9/bitsy/l.s:153,201 (short | long)
2000/0904    
	WORD	$_vfiq(SB)		/* FIQ, switch to svc mode */
2000/0831    
2000/1001    
TEXT _vrst(SB), $-4 
	BL	reset
2000/1002    
	BL	reset(SB)
2000/1001    
 
TEXT _vsvc(SB), $-4			/* SWI */
2000/0904    
	SUB	$12, R13		/* make room for pc, psr, & type */ 
	MOVW	R14, 8(R13)		/* ureg->pc = interupted PC */
2000/1002    
	MOVW.DB.W R14, (R13)		/* ureg->pc = interupted PC */
2000/0904    
	MOVW	SPSR, R14		/* ureg->psr = SPSR */ 
	MOVW	R14, 4(R13)		/* ... */
2000/1002    
	MOVW.DB.W R14, (R13)		/* ... */
2000/0904    
	MOVW	$PsrMsvc, R14		/* ureg->type = PsrMsvc */ 
	MOVW	R14, (R13)		/* ... */
2000/1002    
	MOVW.DB.W R14, (R13)		/* ... */
2000/0904    
	MOVM.DB.W.S [R0-R14], (R13)	/* save user level registers, at end r13 points to ureg */ 
	B	_vexcep			/* call the exception handler */
2000/1002    
	MOVW	$setR12(SB), R12	/* Make sure we've got the kernel's SB loaded */ 
	MOVW	R13, R0			/* first arg is pointer to ureg */ 
	SUB	$8, R13			/* space for argument+link */
2000/0831    
2000/1002    
	BL	syscall(SB) 
 
	ADD	$(8+4*15), R13		/* make r13 point to ureg->type */ 
	MOVW	8(R13), R14		/* restore link */ 
	MOVW	4(R13), R0		/* restore SPSR */ 
	MOVW	R0, SPSR		/* ... */ 
	MOVM.DB.S (R13), [R0-R14]	/* restore registers */ 
	ADD	$8, R13			/* pop past ureg->{type+psr} */ 
	RFE				/* MOVM.IA.S.W (R13), [R15] */
2000/0904    
TEXT _vund(SB), $-4			/* undefined */ 
	MOVM.IA	[R0-R3], (R13)		/* free some working space */
2000/1002    
	MOVM.IA	[R0-R4], (R13)		/* free some working space */
2000/0831    
	MOVW	$PsrMund, R0 
	B	_vswitch
2000/1001    
TEXT _vabt(SB), $-4			/* prefetch abort */
2000/0904    
	MOVM.IA	[R0-R3], (R13)		/* free some working space */
2000/1002    
	MOVM.IA	[R0-R4], (R13)		/* free some working space */
2000/0904    
	MOVW	$PsrMabt, R0		/* r0 = type */
2000/0831    
	B	_vswitch
2000/0904    
TEXT _virq(SB), $-4			/* IRQ */ 
	MOVM.IA	[R0-R3], (R13)		/* free some working space */
2000/1002    
	MOVM.IA	[R0-R4], (R13)		/* free some working space */
2000/0904    
	MOVW	$PsrMirq, R0		/* r0 = type */
2000/0831    
	B	_vswitch
2000/0904    
TEXT _vfiq(SB), $-4			/* FIQ */ 
	RFE				/* RIQ is special, ignore it for now */ 
                 
2000/0903    
	/* 
	 *  come here with type in R0 and R13 pointing above saved [r0-r3]
2000/1002    
	 *  come here with type in R0 and R13 pointing above saved [r0-r4] 
	 *  and type in r0.  we'll switch to SVC mode and then call trap.
2000/0903    
	 */
2000/0831    
_vswitch:				/* switch to svc, type in R0 */
2000/1002    
_vswitch:
2000/0904    
	MOVW	SPSR, R1		/* save SPSR for ureg */ 
	MOVW	R14, R2			/* save interrupted pc for ureg */ 
	MOVW	R13, R3			/* save pointer to where the original [R0-R3] are */
2000/1001/sys/src/9/bitsy/l.s:197,235 – 2000/1002/sys/src/9/bitsy/l.s:206,261
2000/0831    
	ORR	$(PsrDirq|PsrDfiq|PsrMsvc), R14 
	MOVW	R14, CPSR
2000/0904    
	/* 
	 *  R13 and R14 is now R13_SVC and R14_SVC.  The values of the previous mode's 
	 *  R13 and R14 are no longer accessible.  That's why R3 was left to point to where 
	 *  the old [r0-r3] are stored. 
	 */
2000/1002    
	/* interupted code kernel or user? */ 
	AND.S	$0xf, R1, R4 
	B.EQ	_userexcep 
 
	/* here for trap from SVC mode */
2000/1001    
	MOVM.DB.W [R0-R2], (R13)	/* set ureg->{type, psr, pc}; r13 points to ureg->type  */
2000/0903    
	MOVM.IA	  (R3), [R0-R3]		/* restore [R0-R3] from previous mode's stack */
2000/0904    
	MOVM.DB.W.S [R0-R14], (R13)	/* save user level registers, at end r13 points to ureg */
2000/1002    
	MOVM.IA	  (R3), [R0-R4]		/* restore [R0-R4] from previous mode's stack */ 
	MOVM.DB.W [R0-R14], (R13)	/* save kernel level registers, at end r13 points to ureg */ 
	MOVW	$setR12(SB), R12	/* Make sure we've got the kernel's SB loaded */ 
	MOVW	R13, R0			/* first arg is pointer to ureg */ 
	SUB	$8, R13			/* space for argument+link (for debugger) */
2000/0831    
2000/0904    
	/*
2000/1001    
	 *  if the original interrupt happened while executing SVC mode, 
	 *  the User R14 in the Ureg is wrong.  We need to save the SVC one there.
2000/0903    
	 */
2000/0904    
	MOVW	0x40(R13), R1 
	AND.S	$0xf, R1 
	MOVW.NE	R14,0x38(R13) 
	B	_vexcep
2000/1002    
	BL	trap(SB)
2000/0831    
2000/0904    
	/* 
 	 *  call the exception routine, the ureg is at the bottom of the stack 
	 */ 
_vexcep:
2000/1002    
	ADD	$(8+4*15), R13		/* make r13 point to ureg->type */ 
	MOVW	8(R13), R14		/* restore link */ 
	MOVW	4(R13), R0		/* restore SPSR */ 
	MOVW	R0, SPSR		/* ... */ 
	MOVM.DB (R13), [R0-R14]	/* restore registers */ 
	ADD	$8, R13			/* pop past ureg->{type+psr} */ 
	RFE				/* MOVM.IA.S.W (R13), [R15] */ 
 
	/* here for trap from USER mode */ 
_userexcep: 
	MOVM.DB.W [R0-R2], (R13)	/* set ureg->{type, psr, pc}; r13 points to ureg->type  */ 
	MOVM.IA	  (R3), [R0-R4]		/* restore [R0-R4] from previous mode's stack */ 
	MOVM.DB.W.S [R0-R14], (R13)	/* save kernel level registers, at end r13 points to ureg */
2000/0904    
	MOVW	$setR12(SB), R12	/* Make sure we've got the kernel's SB loaded */
2000/0903    
	MOVW	R13, R0			/* first arg is pointer to ureg */
2000/0831    
	SUB	$8, R13			/* space for argument+link */
2000/1002    
	SUB	$8, R13			/* space for argument+link (for debugger) */
2000/0929    
	BL	trap(SB)
2000/0831    
2000/0903    
_vrfe:
2000/0904    
	ADD	$(8+4*15), R13		/* make r13 point to ureg->type */
2000/0903    
	MOVW	8(R13), R14		/* restore link */ 
	MOVW	4(R13), R0		/* restore SPSR */ 
	MOVW	R0, SPSR		/* ... */
2000/1001    
	MOVM.DB.W.S (R13), [R0-R14]	/* restore registers */
2000/1002    
	MOVM.DB.S (R13), [R0-R14]	/* restore registers */ 
	ADD	$8, R13			/* pop past ureg->{type+psr} */ 
	RFE				/* MOVM.IA.S.W (R13), [R15] */ 
 
TEXT _vfiq(SB), $-4			/* FIQ */ 
	RFE				/* FIQ is special, ignore it for now */ 
 
TEXT forkret(SB),$-4 
	ADD	$(4*15), R13		/* make r13 point to ureg->type */ 
	MOVW	8(R13), R14		/* restore link */ 
	MOVW	4(R13), R0		/* restore SPSR */ 
	MOVW	R0, SPSR		/* ... */ 
	MOVM.DB.S (R13), [R0-R14]	/* restore registers */
2000/0904    
	ADD	$8, R13			/* pop past ureg->{type+psr} */
2000/0831    
	RFE				/* MOVM.IA.S.W (R13), [R15] */
2000/1002/sys/src/9/bitsy/l.s:10,18 – 2000/1007/sys/src/9/bitsy/l.s:10,22 (short | long)
2000/0901    
	MOVW	$(PsrDirq|PsrDfiq|PsrMsvc), R1
2000/0831    
	MOVW	R1, CPSR
2000/0901    
2000/0905    
	/* flush TLB's */ 
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0x0) 
	/* drain prefetch */
2000/1007    
	/* disable the MMU */ 
	MOVW	$0x130, R1 
	MCR     CpMMU, 0, R1, C(CpControl), C(0x0) 
 
	/* flush caches */ 
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0x7), 0 
	/* drain prefetch */
2000/0905    
	MOVW	R0,R0						 
	MOVW	R0,R0 
	MOVW	R0,R0
2000/1002/sys/src/9/bitsy/l.s:19,30 – 2000/1007/sys/src/9/bitsy/l.s:23,30
2000/0905    
	MOVW	R0,R0
2000/0901    
2000/0905    
	/* drain write buffer */ 
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0x0), 4
2000/1007    
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0xa), 4
2000/0905    
 
	/* disable the MMU */ 
	MOVW	$0x130, R1 
	MCR     CpMMU, 0, R1, C(CpControl), C(0x0)
2000/0902    
                 
2000/0831    
	MOVW	$(MACHADDR+BY2PG), R13		/* stack */ 
	SUB	$4, R13				/* link */ 
	BL	main(SB)
2000/1002/sys/src/9/bitsy/l.s:36,47 – 2000/1007/sys/src/9/bitsy/l.s:36,47
2000/0831    
2000/0901    
/* flush tlb's */ 
TEXT flushmmu(SB), $-4 
	MCR	CpMMU, 0, R0, C(CpTLBFlush), C(0x0)
2000/1007    
	MCR	CpMMU, 0, R0, C(CpTLBFlush), C(0x7)
2000/0831    
	RET
2000/0901    
/* flush instruction cache */ 
TEXT flushicache(SB), $-4 
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0x0)
2000/1007    
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0x5), 0
2000/0901    
	/* drain prefetch */ 
	MOVW	R0,R0					 
	MOVW	R0,R0
2000/1002/sys/src/9/bitsy/l.s:51,62 – 2000/1007/sys/src/9/bitsy/l.s:51,62
2000/0831    
2000/0901    
/* flush data cache */ 
TEXT flushdcache(SB), $-4 
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0x0)
2000/1007    
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0x6), 0
2000/0831    
	RET
2000/0901    
/* flush i and d caches */ 
TEXT flushcache(SB), $-4 
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0x0)
2000/1007    
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0x7), 0
2000/0901    
	/* drain prefetch */ 
	MOVW	R0,R0						 
	MOVW	R0,R0
2000/1002/sys/src/9/bitsy/l.s:66,72 – 2000/1007/sys/src/9/bitsy/l.s:66,72
2000/0831    
2000/0901    
/* drain write buffer */
2000/0929    
TEXT wbflush(SB), $-4
2000/0901    
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0x0), 4
2000/1007    
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0xa), 4
2000/0831    
	RET
2000/0901    
/* return cpu id */
2000/1002/sys/src/9/bitsy/l.s:90,100 – 2000/1007/sys/src/9/bitsy/l.s:90,100
2000/0929    
	RET
2000/0906    
2000/0929    
/* 
 *  enable mmu, i and d caches, and exception vectors at 0xffff0000
2000/1007    
 *  enable mmu, i and d caches
2000/0929    
 */ 
TEXT mmuenable(SB), $-4 
	MRC	CpMMU, 0, R0, C(CpControl), C(0x0) 
	ORR	$(CpCmmuena|CpCdcache|CpCicache|CpCvivec), R0
2000/1007    
	ORR	$(CpCmmuena|CpCdcache|CpCicache), R0
2000/0929    
	MCR     CpMMU, 0, R0, C(CpControl), C(0x0) 
	RET
2000/1002/sys/src/9/bitsy/l.s:104,109 – 2000/1007/sys/src/9/bitsy/l.s:104,123
2000/0929    
	MCR     CpMMU, 0, R0, C(CpControl), C(0x0) 
	RET
2000/1007    
/* 
 *  use exception vectors at 0xffff0000 
 */ 
TEXT mappedIvecEnable(SB), $-4 
	MRC	CpMMU, 0, R0, C(CpControl), C(0x0) 
	ORR	$(CpCvivec), R0 
	MCR     CpMMU, 0, R0, C(CpControl), C(0x0) 
	RET 
TEXT mappedIvecDisable(SB), $-4 
	MRC	CpMMU, 0, R0, C(CpControl), C(0x0) 
	BIC	$(CpCvivec), R0 
	MCR     CpMMU, 0, R0, C(CpControl), C(0x0) 
	RET
2000/0906    
/* set the translation table base */ 
TEXT putdac(SB), $-4 
	MCR	CpMMU, 0, R0, C(CpDAC), C(0x0)
2000/1002/sys/src/9/bitsy/l.s:134,156 – 2000/1007/sys/src/9/bitsy/l.s:148,173
2000/0904    
/* 
 *  exception vectors, copied by trapinit() to somewhere useful 
 */
2000/0929    
TEXT exceptionvectors(SB), $-4
2000/0904    
	MOVW	0x18(R15), R15		/* reset */ 
	MOVW	0x18(R15), R15		/* undefined */ 
	MOVW	0x18(R15), R15		/* SWI */ 
	MOVW	0x18(R15), R15		/* prefetch abort */ 
	MOVW	0x18(R15), R15		/* data abort */ 
	MOVW	0x18(R15), R15		/* reserved */ 
	MOVW	0x18(R15), R15		/* IRQ */ 
	MOVW	0x18(R15), R15		/* FIQ */
2000/1001    
	WORD	$_vrst(SB)		/* reset, in svc mode already */
2000/0904    
	WORD	$_vund(SB)		/* undefined, switch to svc mode */ 
	WORD	$_vsvc(SB)		/* swi, in svc mode already */
2000/1001    
	WORD	$_vabt(SB)		/* prefetch abort, switch to svc mode */ 
	WORD	$_vabt(SB)		/* data abort, switch to svc mode */ 
	WORD	$_vrst(SB)		/* reserved, shouldn't happen */
2000/0904    
	WORD	$_virq(SB)		/* IRQ, switch to svc mode */ 
	WORD	$_vfiq(SB)		/* FIQ, switch to svc mode */
2000/1007    
 
TEXT vectors(SB), $-4 
	MOVW	0x18(R15), R15			/* reset */ 
	MOVW	0x18(R15), R15			/* undefined */ 
	MOVW	0x18(R15), R15			/* SWI */ 
	MOVW	0x18(R15), R15			/* prefetch abort */ 
	MOVW	0x18(R15), R15			/* data abort */ 
	MOVW	0x18(R15), R15			/* reserved */ 
	MOVW	0x18(R15), R15			/* IRQ */ 
	MOVW	0x18(R15), R15			/* FIQ */ 
 
TEXT vtable(SB), $-4 
	WORD	$_vsvc(SB)			/* reset, in svc mode already */ 
	WORD	$_vund(SB)			/* undefined, switch to svc mode */ 
	WORD	$_vsvc(SB)			/* swi, in svc mode already */ 
	WORD	$_vabt(SB)			/* prefetch abort, switch to svc mode */ 
	WORD	$_vabt(SB)			/* data abort, switch to svc mode */ 
	WORD	$_vsvc(SB)			/* reserved */ 
	WORD	$_virq(SB)			/* IRQ, switch to svc mode */ 
	WORD	$_vfiq(SB)			/* FIQ, switch to svc mode */
2000/0831    
2000/1001    
TEXT _vrst(SB), $-4
2000/1002    
	BL	reset(SB)
2000/1007/sys/src/9/bitsy/l.s:56,62 – 2000/1010/sys/src/9/bitsy/l.s:56,72 (short | long)
2000/0831    
2000/0901    
/* flush i and d caches */ 
TEXT flushcache(SB), $-4
2000/1010    
	/* write back any dirty data */ 
	MOVW	$0xe0000000,R0 
	ADD	$(8*1024),R0,R1 
_wbloop: 
	MOVW.W	32(R0),R2 
	CMP	R0,R1 
	BNE	_wbloop 
	 
	/* flush cache contents */
2000/1007    
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0x7), 0
2000/1010    
2000/0901    
	/* drain prefetch */ 
	MOVW	R0,R0						 
	MOVW	R0,R0
2000/1007/sys/src/9/bitsy/l.s:225,231 – 2000/1010/sys/src/9/bitsy/l.s:235,241
2000/0831    
2000/1002    
	/* interupted code kernel or user? */ 
	AND.S	$0xf, R1, R4 
	B.EQ	_userexcep
2000/1010    
	BEQ	_userexcep
2000/1002    
 
	/* here for trap from SVC mode */
2000/1001    
	MOVM.DB.W [R0-R2], (R13)	/* set ureg->{type, psr, pc}; r13 points to ureg->type  */
2000/1010/sys/src/9/bitsy/l.s:173,180 – 2000/1012/sys/src/9/bitsy/l.s:173,180 (short | long)
2000/1007    
	WORD	$_vsvc(SB)			/* reset, in svc mode already */ 
	WORD	$_vund(SB)			/* undefined, switch to svc mode */ 
	WORD	$_vsvc(SB)			/* swi, in svc mode already */ 
	WORD	$_vabt(SB)			/* prefetch abort, switch to svc mode */ 
	WORD	$_vabt(SB)			/* data abort, switch to svc mode */
2000/1012    
	WORD	$_vpabt(SB)			/* prefetch abort, switch to svc mode */ 
	WORD	$_vdabt(SB)			/* data abort, switch to svc mode */
2000/1007    
	WORD	$_vsvc(SB)			/* reserved */ 
	WORD	$_virq(SB)			/* IRQ, switch to svc mode */ 
	WORD	$_vfiq(SB)			/* FIQ, switch to svc mode */
2000/1010/sys/src/9/bitsy/l.s:208,218 – 2000/1012/sys/src/9/bitsy/l.s:208,223
2000/0831    
	MOVW	$PsrMund, R0 
	B	_vswitch
2000/1001    
TEXT _vabt(SB), $-4			/* prefetch abort */
2000/1012    
TEXT _vpabt(SB), $-4			/* prefetch abort */
2000/1002    
	MOVM.IA	[R0-R4], (R13)		/* free some working space */
2000/0904    
	MOVW	$PsrMabt, R0		/* r0 = type */
2000/0831    
	B	_vswitch
2000/1012    
TEXT _vdabt(SB), $-4			/* prefetch abort */ 
	MOVM.IA	[R0-R4], (R13)		/* free some working space */ 
	MOVW	$(PsrMabt+1), R0		/* r0 = type */ 
	B	_vswitch
2000/0904    
TEXT _virq(SB), $-4			/* IRQ */
2000/1002    
	MOVM.IA	[R0-R4], (R13)		/* free some working space */
2000/0904    
	MOVW	$PsrMirq, R0		/* r0 = type */
2000/1010/sys/src/9/bitsy/l.s:277,282 – 2000/1012/sys/src/9/bitsy/l.s:282,314
2000/1002    
TEXT _vfiq(SB), $-4			/* FIQ */ 
	RFE				/* FIQ is special, ignore it for now */
2000/1012    
/* 
 *  This is the first jump from kernel to user mode. 
 *  Fake a return from interrupt. 
 * 
 *  Enter with R0 containing the user stack pointer. 
 *  UTZERO + 0x20 is always the entry point. 
 *   
 */ 
TEXT touser(SB),$-4 
	/* store the user stack pointer into the USR_r13 */ 
	MOVM.DB.W [R0], (R13) 
	MOVM.S.IA.W (R13),[R13] 
 
	/* set up a PSR for user level */ 
	MOVW	$(PsrMusr), R0 
	MOVW	R0,SPSR 
 
	/* save the PC on the stack */ 
	MOVW	$(UTZERO+0x20), R0 
	MOVM.DB.W [R0],(R13) 
 
	/* return from interrupt */ 
	RFE				/* MOVM.IA.S.W (R13), [R15] */ 
	 
/* 
 *  here to jump to a newly forked process 
 */
2000/1002    
TEXT forkret(SB),$-4 
	ADD	$(4*15), R13		/* make r13 point to ureg->type */ 
	MOVW	8(R13), R14		/* restore link */
2000/1012/sys/src/9/bitsy/l.s:39,59 – 2000/1013/sys/src/9/bitsy/l.s:39,44 (short | long)
2000/1007    
	MCR	CpMMU, 0, R0, C(CpTLBFlush), C(0x7)
2000/0831    
	RET
2000/0901    
/* flush instruction cache */ 
TEXT flushicache(SB), $-4
2000/1007    
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0x5), 0
2000/0901    
	/* drain prefetch */ 
	MOVW	R0,R0					 
	MOVW	R0,R0 
	MOVW	R0,R0 
	MOVW	R0,R0
2000/0831    
	RET 
                 
2000/0901    
/* flush data cache */ 
TEXT flushdcache(SB), $-4
2000/1007    
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0x6), 0
2000/0831    
	RET 
                 
2000/0901    
/* flush i and d caches */ 
TEXT flushcache(SB), $-4
2000/1010    
	/* write back any dirty data */
2000/1012/sys/src/9/bitsy/l.s:72,78 – 2000/1013/sys/src/9/bitsy/l.s:57,62
2000/0901    
	MOVW	R0,R0 
	MOVW	R0,R0 
	MOVW	R0,R0
2000/0831    
	RET
2000/0901    
/* drain write buffer */
2000/0929    
TEXT wbflush(SB), $-4
2000/1012/sys/src/9/bitsy/l.s:104,116 – 2000/1013/sys/src/9/bitsy/l.s:88,100
2000/0929    
 */ 
TEXT mmuenable(SB), $-4 
	MRC	CpMMU, 0, R0, C(CpControl), C(0x0)
2000/1007    
	ORR	$(CpCmmuena|CpCdcache|CpCicache), R0
2000/1013    
	ORR	$(CpCmmuena), R0
2000/0929    
	MCR     CpMMU, 0, R0, C(CpControl), C(0x0) 
	RET 
 
TEXT mmudisable(SB), $-4 
	MRC	CpMMU, 0, R0, C(CpControl), C(0x0) 
	BIC	$(CpCmmuena|CpCdcache|CpCicache|CpCvivec), R0
2000/1013    
	BIC	$(CpCmmuena|CpCvivec), R0
2000/0929    
	MCR     CpMMU, 0, R0, C(CpControl), C(0x0) 
	RET
2000/1012/sys/src/9/bitsy/l.s:387,399 – 2000/1013/sys/src/9/bitsy/l.s:371,373
2000/0831    
	MOVW	4(R0), R14			/* pc */ 
	MOVW	$1, R0 
	RET 
                 
TEXT mmuctlregr(SB), $-4 
	MRC		CpMMU, 0, R0, C(CpControl), C(0) 
	RET	 
                 
TEXT mmuctlregw(SB), $-4 
	MCR		CpMMU, 0, R0, C(CpControl), C(0) 
	MOVW		R0, R0 
	MOVW		R0, R0 
	RET
2000/1013/sys/src/9/bitsy/l.s:39,46 – 2000/1014/sys/src/9/bitsy/l.s:39,46 (short | long)
2000/1007    
	MCR	CpMMU, 0, R0, C(CpTLBFlush), C(0x7)
2000/0831    
	RET
2000/0901    
/* flush i and d caches */ 
TEXT flushcache(SB), $-4
2000/1014    
/* clean and flush i and d caches */ 
TEXT cleancache(SB), $-4
2000/1010    
	/* write back any dirty data */ 
	MOVW	$0xe0000000,R0 
	ADD	$(8*1024),R0,R1
2000/1013/sys/src/9/bitsy/l.s:57,63 – 2000/1014/sys/src/9/bitsy/l.s:57,81
2000/0901    
	MOVW	R0,R0 
	MOVW	R0,R0 
	MOVW	R0,R0
2000/1014    
	RET
2000/0831    
2000/1014    
/* clean a single virtual address */ 
TEXT cleanaddr(SB), $-4 
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0xa), 1 
	RET 
 
/* flush i and d caches */ 
TEXT flushcache(SB), $-4 
	/* flush cache contents */ 
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0x7), 0 
 
	/* drain prefetch */ 
	MOVW	R0,R0						 
	MOVW	R0,R0 
	MOVW	R0,R0 
	MOVW	R0,R0 
	RET
2000/0901    
/* drain write buffer */
2000/0929    
TEXT wbflush(SB), $-4
2000/1007    
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0xa), 4
2000/1013/sys/src/9/bitsy/l.s:78,83 – 2000/1014/sys/src/9/bitsy/l.s:96,106
2000/0901    
	MRC	CpMMU, 0, R0, C(CpFAR), C(0x0)
2000/0831    
	RET
2000/1014    
/* return fault address */ 
TEXT putfar(SB), $-4 
	MRC	CpMMU, 0, R0, C(CpFAR), C(0x0) 
	RET
2000/0904    
/* set the translation table base */
2000/0906    
TEXT putttb(SB), $-4
2000/0901    
	MCR	CpMMU, 0, R0, C(CpTTB), C(0x0)
2000/1013/sys/src/9/bitsy/l.s:167,177 – 2000/1014/sys/src/9/bitsy/l.s:190,200
2000/1002    
	BL	reset(SB)
2000/1001    
 
TEXT _vsvc(SB), $-4			/* SWI */
2000/1002    
	MOVW.DB.W R14, (R13)		/* ureg->pc = interupted PC */
2000/1014    
	MOVW.W	R14, -4(R13)		/* ureg->pc = interupted PC */
2000/0904    
	MOVW	SPSR, R14		/* ureg->psr = SPSR */
2000/1002    
	MOVW.DB.W R14, (R13)		/* ... */
2000/1014    
	MOVW.W	R14, -4(R13)		/* ... */
2000/0904    
	MOVW	$PsrMsvc, R14		/* ureg->type = PsrMsvc */
2000/1002    
	MOVW.DB.W R14, (R13)		/* ... */
2000/1014    
	MOVW.W	R14, -4(R13)		/* ... */
2000/0904    
	MOVM.DB.W.S [R0-R14], (R13)	/* save user level registers, at end r13 points to ureg */
2000/1002    
	MOVW	$setR12(SB), R12	/* Make sure we've got the kernel's SB loaded */ 
	MOVW	R13, R0			/* first arg is pointer to ureg */
2000/1014/sys/src/9/bitsy/l.s:35,46 – 2000/1015/sys/src/9/bitsy/l.s:35,46 (short | long)
2000/0904    
	BL	_div(SB)			/* hack to get _div etc loaded */
2000/0831    
2000/0901    
/* flush tlb's */ 
TEXT flushmmu(SB), $-4
2000/1015    
TEXT mmuinvalidate(SB), $-4
2000/1007    
	MCR	CpMMU, 0, R0, C(CpTLBFlush), C(0x7)
2000/0831    
	RET
2000/1014    
/* clean and flush i and d caches */ 
TEXT cleancache(SB), $-4
2000/1015    
/* write back and invalidate i and d caches */ 
TEXT cacheflush(SB), $-4
2000/1010    
	/* write back any dirty data */ 
	MOVW	$0xe0000000,R0 
	ADD	$(8*1024),R0,R1
2000/1014/sys/src/9/bitsy/l.s:49,55 – 2000/1015/sys/src/9/bitsy/l.s:49,56
2000/1010    
	CMP	R0,R1 
	BNE	_wbloop 
	 
	/* flush cache contents */
2000/1015    
	/* drain write buffer and flush i&d cache contents */ 
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0xa), 4
2000/1007    
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0x7), 0
2000/1010    
2000/0901    
	/* drain prefetch */
2000/1014/sys/src/9/bitsy/l.s:60,81 – 2000/1015/sys/src/9/bitsy/l.s:61,70
2000/1014    
	RET
2000/0831    
2000/1014    
/* clean a single virtual address */ 
TEXT cleanaddr(SB), $-4
2000/1015    
TEXT cacheflushaddr(SB), $-4
2000/1014    
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0xa), 1 
	RET 
 
/* flush i and d caches */ 
TEXT flushcache(SB), $-4 
	/* flush cache contents */ 
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0x7), 0 
                 
	/* drain prefetch */ 
	MOVW	R0,R0						 
	MOVW	R0,R0 
	MOVW	R0,R0 
	MOVW	R0,R0 
	RET 
                 
2000/0901    
/* drain write buffer */
2000/0929    
TEXT wbflush(SB), $-4
2000/1007    
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0xa), 4
2000/1014/sys/src/9/bitsy/l.s:111,123 – 2000/1015/sys/src/9/bitsy/l.s:100,112
2000/0929    
 */ 
TEXT mmuenable(SB), $-4 
	MRC	CpMMU, 0, R0, C(CpControl), C(0x0)
2000/1013    
	ORR	$(CpCmmuena), R0
2000/1015    
	ORR	$(CpCmmuena|CpCwb|CpCdcache), R0
2000/0929    
	MCR     CpMMU, 0, R0, C(CpControl), C(0x0) 
	RET 
 
TEXT mmudisable(SB), $-4 
	MRC	CpMMU, 0, R0, C(CpControl), C(0x0)
2000/1013    
	BIC	$(CpCmmuena|CpCvivec), R0
2000/1015    
	BIC	$(CpCmmuena|CpCdcache|CpCwb|CpCvivec), R0
2000/0929    
	MCR     CpMMU, 0, R0, C(CpControl), C(0x0) 
	RET
2000/1015/sys/src/9/bitsy/l.s:39,55 – 2000/1018/sys/src/9/bitsy/l.s:39,60 (short | long)
2000/1007    
	MCR	CpMMU, 0, R0, C(CpTLBFlush), C(0x7)
2000/0831    
	RET
2000/1018    
/* flush tlb's */ 
TEXT mmuinvalidateaddr(SB), $-4 
	MCR	CpMMU, 0, R0, C(CpTLBFlush), C(0x6), 1 
	RET
2000/1015    
/* write back and invalidate i and d caches */ 
TEXT cacheflush(SB), $-4
2000/1010    
	/* write back any dirty data */ 
	MOVW	$0xe0000000,R0 
	ADD	$(8*1024),R0,R1 
_wbloop: 
	MOVW.W	32(R0),R2
2000/1018    
_cfloop: 
	MOVW.P	32(R0),R2
2000/1010    
	CMP	R0,R1 
	BNE	_wbloop
2000/1018    
	BNE	_cfloop
2000/1010    
2000/1015    
	/* drain write buffer and flush i&d cache contents */
2000/1018    
	/* drain write buffer and invalidate i&d cache contents */
2000/1015    
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0xa), 4
2000/1007    
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0x7), 0
2000/1010    
2000/1015/sys/src/9/bitsy/l.s:60,72 – 2000/1018/sys/src/9/bitsy/l.s:65,116
2000/0901    
	MOVW	R0,R0
2000/1014    
	RET
2000/0831    
2000/1014    
/* clean a single virtual address */
2000/1015    
TEXT cacheflushaddr(SB), $-4
2000/1018    
/* write back and invalidate i and d caches */ 
TEXT cachewb(SB), $-4 
	/* write back any dirty data */ 
	MOVW	$0xe0000000,R0 
	ADD	$(8*1024),R0,R1 
_cwbloop: 
	MOVW.P	32(R0),R2 
	CMP	R0,R1 
	BNE	_cfloop 
	 
	/* drain write buffer */ 
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0xa), 4 
	RET 
 
/* write back a single cache line */ 
TEXT cachewbaddr(SB), $-4 
	BIC	$31,R0
2000/1014    
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0xa), 1
2000/1018    
	B	_wbflush 
 
/* write back a region of cache lines */ 
TEXT cachewbregion(SB), $-4 
	MOVW	4(FP),R1 
	BIC	$31,R0 
	ADD	R0,R1 
	ADD	$32,R1 
_cfrloop: 
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0xa), 1 
	ADD	$32,R0 
	CMP.S	R0,R1 
	BNE	_cfrloop 
	B	_wbflush 
 
/* invalidate the dcache */ 
TEXT dcacheinvalidate(SB), $-4 
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0x6)
2000/1014    
	RET
2000/1018    
/* invalidate the icache */ 
TEXT icacheinvalidate(SB), $-4 
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0x9) 
	RET
2000/0901    
/* drain write buffer */
2000/0929    
TEXT wbflush(SB), $-4
2000/1018    
_wbflush:
2000/1007    
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0xa), 4
2000/0831    
	RET
2000/1015/sys/src/9/bitsy/l.s:100,106 – 2000/1018/sys/src/9/bitsy/l.s:144,150
2000/0929    
 */ 
TEXT mmuenable(SB), $-4 
	MRC	CpMMU, 0, R0, C(CpControl), C(0x0)
2000/1015    
	ORR	$(CpCmmuena|CpCwb|CpCdcache), R0
2000/1018    
	ORR	$(CpCmmuena|CpCdcache|CpCwb), R0
2000/0929    
	MCR     CpMMU, 0, R0, C(CpControl), C(0x0) 
	RET
2000/1018/sys/src/9/bitsy/l.s:289,294 – 2000/1028/sys/src/9/bitsy/l.s:289,295 (short | long)
2000/1002    
	MOVW	$setR12(SB), R12	/* Make sure we've got the kernel's SB loaded */ 
	MOVW	R13, R0			/* first arg is pointer to ureg */ 
	SUB	$8, R13			/* space for argument+link (for debugger) */
2000/1028    
	MOVW	$0xdeaddead,R11		/* marker */
2000/0831    
2000/1002    
	BL	trap(SB)
2000/0831    
2000/1028/sys/src/9/bitsy/l.s:144,156 – 2000/1101/sys/src/9/bitsy/l.s:144,156 (short | long)
2000/0929    
 */ 
TEXT mmuenable(SB), $-4 
	MRC	CpMMU, 0, R0, C(CpControl), C(0x0)
2000/1018    
	ORR	$(CpCmmuena|CpCdcache|CpCwb), R0
2000/1101    
	ORR	$(CpCmmuena|CpCdcache|CpCicache|CpCwb), R0
2000/0929    
	MCR     CpMMU, 0, R0, C(CpControl), C(0x0) 
	RET 
 
TEXT mmudisable(SB), $-4 
	MRC	CpMMU, 0, R0, C(CpControl), C(0x0)
2000/1015    
	BIC	$(CpCmmuena|CpCdcache|CpCwb|CpCvivec), R0
2000/1101    
	BIC	$(CpCmmuena|CpCdcache|CpCicache|CpCwb|CpCvivec), R0
2000/0929    
	MCR     CpMMU, 0, R0, C(CpControl), C(0x0) 
	RET
2000/1028/sys/src/9/bitsy/l.s:360,365 – 2000/1101/sys/src/9/bitsy/l.s:360,369
2000/0831    
	RFE				/* MOVM.IA.S.W (R13), [R15] */ 
 
TEXT splhi(SB), $-4
2000/1101    
	/* save caller pc in Mach */ 
	MOVW	$(MACHADDR+0x04),R2 
	MOVW	R14,0(R2) 
	/* turn off interrupts */
2000/0831    
	MOVW	CPSR, R0 
	ORR	$(PsrDfiq|PsrDirq), R0, R1 
	MOVW	R1, CPSR
2000/1028/sys/src/9/bitsy/l.s:372,377 – 2000/1101/sys/src/9/bitsy/l.s:376,385
2000/0831    
	RET 
 
TEXT splx(SB), $-4
2000/1101    
	/* save caller pc in Mach */ 
	MOVW	$(MACHADDR+0x04),R2 
	MOVW	R14,0(R2) 
	/* reset interrupt level */
2000/0902    
	MOVW	R0, R1 
	MOVW	CPSR, R0 
	MOVW	R1, CPSR
2000/1028/sys/src/9/bitsy/l.s:381,386 – 2000/1101/sys/src/9/bitsy/l.s:389,397
2000/0831    
	MOVW	R0, R1 
	MOVW	CPSR, R0 
	MOVW	R1, CPSR
2000/1101    
	RET 
 
TEXT spldone(SB), $0
2000/0831    
	RET 
 
TEXT islo(SB), $-4
2000/1101/sys/src/9/bitsy/l.s:65,71 – 2000/1102/sys/src/9/bitsy/l.s:65,71 (short | long)
2000/0901    
	MOVW	R0,R0
2000/1014    
	RET
2000/0831    
2000/1018    
/* write back and invalidate i and d caches */
2000/1102    
/* write back d cache */
2000/1018    
TEXT cachewb(SB), $-4 
	/* write back any dirty data */ 
	MOVW	$0xe0000000,R0
2000/1102/sys/src/9/bitsy/l.s:51,57 – 2000/1106/sys/src/9/bitsy/l.s:51,57 (short | long)
2000/1010    
	ADD	$(8*1024),R0,R1
2000/1018    
_cfloop: 
	MOVW.P	32(R0),R2
2000/1010    
	CMP	R0,R1
2000/1106    
	CMP.S	R0,R1
2000/1018    
	BNE	_cfloop
2000/1010    
2000/1018    
	/* drain write buffer and invalidate i&d cache contents */
2000/1102/sys/src/9/bitsy/l.s:68,79 – 2000/1106/sys/src/9/bitsy/l.s:68,80
2000/1102    
/* write back d cache */
2000/1018    
TEXT cachewb(SB), $-4 
	/* write back any dirty data */
2000/1106    
_cachewb:
2000/1018    
	MOVW	$0xe0000000,R0 
	ADD	$(8*1024),R0,R1 
_cwbloop: 
	MOVW.P	32(R0),R2 
	CMP	R0,R1 
	BNE	_cfloop
2000/1106    
	CMP.S	R0,R1 
	BNE	_cwbloop
2000/1018    
	 
	/* drain write buffer */ 
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0xa), 4
2000/1102/sys/src/9/bitsy/l.s:88,101 – 2000/1106/sys/src/9/bitsy/l.s:89,103
2000/1018    
/* write back a region of cache lines */ 
TEXT cachewbregion(SB), $-4 
	MOVW	4(FP),R1 
	BIC	$31,R0
2000/1106    
	CMP.S	$(4*1024),R1 
	BGT	_cachewb
2000/1018    
	ADD	R0,R1 
	ADD	$32,R1 
_cfrloop:
2000/1106    
	BIC	$31,R0 
_cwbrloop:
2000/1018    
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0xa), 1 
	ADD	$32,R0 
	CMP.S	R0,R1 
	BNE	_cfrloop
2000/1106    
	BGT	_cwbrloop
2000/1018    
	B	_wbflush 
 
/* invalidate the dcache */
2000/1102/sys/src/9/bitsy/l.s:407,422 – 2000/1106/sys/src/9/bitsy/l.s:409,414
2000/0831    
TEXT spsrr(SB), $-4 
	MOVW	SPSR, R0 
	RET 
                 
TEXT aamloop(SB), $-4				/* 3 */ 
_aamloop: 
	MOVW	R0, R0				/* 1 */ 
	MOVW	R0, R0				/* 1 */ 
	MOVW	R0, R0				/* 1 */ 
	SUB	$1, R0				/* 1 */ 
	CMP	$0, R0				/* 1 */ 
	BNE	_aamloop			/* 3 */ 
	RET					/* 3 */ 
 
TEXT getcallerpc(SB), $-4 
	MOVW	0(R13), R0
2000/1106/sys/src/9/bitsy/l.s:431,433 – 2000/1130/sys/src/9/bitsy/l.s:431,454 (short | long)
2000/0831    
	MOVW	4(R0), R14			/* pc */ 
	MOVW	$1, R0 
	RET
2000/1130    
 
 
/* The first MCR instruction of this function needs to be on a cache-line 
 * boundary; to make this happen, it will be copied (in trap.c). 
 * 
 * Doze puts the machine into idle mode.  Any interrupt will get it out 
 * at the next instruction (the RET, to be precise). 
 */ 
TEXT _doze(SB), $-4 
	MOVW	$UCDRAMZERO, R1 
	MOVW	R0,R0 
	MOVW	R0,R0 
	MOVW	R0,R0 
	MOVW	R0,R0 
	MOVW	R0,R0 
	MOVW	R0,R0 
	MOVW	R0,R0 
	MCR     CpPWR, 0, R0, C(CpTest), C(0x2), 2 
	MOVW	(R1), R0 
	MCR     CpPWR, 0, R0, C(CpTest), C(0x8), 2 
	RET
2000/1130/sys/src/9/bitsy/l.s:222,228 – 2000/1205/sys/src/9/bitsy/l.s:222,228 (short | long)
2000/1007    
	WORD	$_vfiq(SB)			/* FIQ, switch to svc mode */
2000/0831    
2000/1001    
TEXT _vrst(SB), $-4
2000/1002    
	BL	reset(SB)
2000/1205    
	BL	resettrap(SB)
2000/1001    
 
TEXT _vsvc(SB), $-4			/* SWI */
2000/1014    
	MOVW.W	R14, -4(R13)		/* ureg->pc = interupted PC */
2000/1205/sys/src/9/bitsy/l.s:25,31 – 2000/1206/sys/src/9/bitsy/l.s:25,31 (short | long)
2000/0905    
	/* drain write buffer */
2000/1007    
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0xa), 4
2000/0905    
2000/0831    
	MOVW	$(MACHADDR+BY2PG), R13		/* stack */
2000/1206    
	MOVW	$(MACHADDR+2*BY2PG), R13		/* stack */
2000/0831    
	SUB	$4, R13				/* link */ 
	BL	main(SB)
2000/0901    
	BL	exit(SB)
2000/1206/sys/src/9/bitsy/l.s:25,31 – 2000/1207/sys/src/9/bitsy/l.s:25,31 (short | long)
2000/0905    
	/* drain write buffer */
2000/1007    
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0xa), 4
2000/0905    
2000/1206    
	MOVW	$(MACHADDR+2*BY2PG), R13		/* stack */
2000/1207    
	MOVW	$(MACHADDR+4*BY2PG), R13		/* stack */
2000/0831    
	SUB	$4, R13				/* link */ 
	BL	main(SB)
2000/0901    
	BL	exit(SB)
2000/1206/sys/src/9/bitsy/l.s:54,62 – 2000/1207/sys/src/9/bitsy/l.s:54,62
2000/1106    
	CMP.S	R0,R1
2000/1018    
	BNE	_cfloop
2000/1010    
2000/1018    
	/* drain write buffer and invalidate i&d cache contents */
2000/1207    
	/* drain write buffer and invalidate i cache contents */
2000/1015    
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0xa), 4
2000/1007    
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0x7), 0
2000/1207    
	MCR	CpMMU, 0, R0, C(CpCacheFlush), C(0x5), 0
2000/1010    
2000/0901    
	/* drain prefetch */ 
	MOVW	R0,R0
2000/1206/sys/src/9/bitsy/l.s:367,379 – 2000/1207/sys/src/9/bitsy/l.s:367,379
2000/1101    
	MOVW	R14,0(R2) 
	/* turn off interrupts */
2000/0831    
	MOVW	CPSR, R0 
	ORR	$(PsrDfiq|PsrDirq), R0, R1
2000/1207    
	ORR	$(PsrDirq), R0, R1
2000/0831    
	MOVW	R1, CPSR 
	RET 
 
TEXT spllo(SB), $-4 
	MOVW	CPSR, R0 
	BIC	$(PsrDfiq|PsrDirq), R0, R1
2000/1207    
	BIC	$(PsrDirq), R0, R1
2000/0831    
	MOVW	R1, CPSR 
	RET
2000/1206/sys/src/9/bitsy/l.s:398,405 – 2000/1207/sys/src/9/bitsy/l.s:398,405
2000/0831    
 
TEXT islo(SB), $-4 
	MOVW	CPSR, R0 
	AND	$(PsrDfiq|PsrDirq), R0 
	EOR	$(PsrDfiq|PsrDirq), R0
2000/1207    
	AND	$(PsrDirq), R0 
	EOR	$(PsrDirq), R0
2000/0831    
	RET 
 
TEXT cpsrr(SB), $-4
2000/1206/sys/src/9/bitsy/l.s:417,423 – 2000/1207/sys/src/9/bitsy/l.s:417,431
2000/0831    
TEXT tas(SB), $-4 
	MOVW	R0, R1 
	MOVW	$0xDEADDEAD, R2
2000/1207    
	MOVW	R2, R3
2000/0831    
	SWPW	R2, (R1), R0
2000/1207    
	CMP.S	R0, R3 
	BEQ	_tasout 
	EOR	R3, R3 
	CMP.S	R0, R3 
	BEQ	_tasout 
	MOVW	$1,R15 
_tasout:
2000/0831    
	RET 
 
TEXT setlabel(SB), $-4
Too many diffs (26 > 25). Stopping.


source code copyright © 1990-2005 Lucent Technologies; see license
Plan 9 distribution
comments to russ cox (rsc@swtch.com)