2002/0110/mtx/ether2114x.c (diff list | history)

2002/0109/sys/src/9/mtx/ether2114x.c:19,25 – 2002/0110/sys/src/9/mtx/ether2114x.c:19,25 (short | long)
2002/0109		#include "etherif.h" #define DEBUG (1)
2002/0110		#define DEBUG (0)
2002/0109		#define debug if(DEBUG)print enum {
2002/0109/sys/src/9/mtx/ether2114x.c:56,62 – 2002/0110/sys/src/9/mtx/ether2114x.c:56,62
2002/0109		Rwt = 0x00000200, /* Receive Watchdog Timeout */ Eti = 0x00000400, /* Early Transmit Interrupt */ Gte = 0x00000800, /* General purpose Timer Expired */ Fbe = 0x00002000, /* Fatal Bit Error */
2002/0110		Fbe = 0x00002000, /* Fatal Bus Error */
2002/0109		Ais = 0x00008000, /* Abnormal Interrupt Summary */ Nis = 0x00010000, /* Normal Interrupt Summary */ Rs = 0x000E0000, /* Receive process State (field) */
2002/0109/sys/src/9/mtx/ether2114x.c:419,425 – 2002/0110/sys/src/9/mtx/ether2114x.c:419,424
2002/0109		Des *des; Block *bp; print("ether intr\n"); ether = arg; ctlr = ether->ctlr;
2002/0109/sys/src/9/mtx/ether2114x.c:800,806 – 2002/0110/sys/src/9/mtx/ether2114x.c:799,805
2002/0109		*/ csr32w(ctlr, 0, Swr); microdelay(10); csr32w(ctlr, 0, Rml|Cal16);
2002/0110		csr32w(ctlr, 0, Rml|Cal16|Dbo);
2002/0109		delay(1); }
2002/0109/sys/src/9/mtx/ether2114x.c:1596,1602 – 2002/0110/sys/src/9/mtx/ether2114x.c:1595,1602
2002/0109		ether->ctlr = ctlr; ether->port = ctlr->port; ether->irq = ctlr->pcidev->intl;
2002/0110		// ether->irq = ctlr->pcidev->intl; ether->irq = 2; /* arrrrrgh */
2002/0109		ether->tbdf = ctlr->pcidev->tbdf; /*
2002/0110/sys/src/9/mtx/ether2114x.c:619,625 – 2002/0711/sys/src/9/mtx/ether2114x.c:619,625 (short | long)
2002/0109		bp->wp += sizeof(bi)*16; ctlr->setupbp = bp; ether->oq = qopen(256*1024, 1, 0, 0);
2002/0711		ether->oq = qopen(256*1024, Qmsg, 0, 0);
2002/0109		transmit(ether); }