pc/l.s		1991/0614		Created.
		1991/0619
		1991/0620
		1991/0622
		1991/0623
		1991/0625
		1991/0626
		1991/0627
		1991/0628
		1991/0629
		1991/0702
		1991/0703
		1991/0704
		1991/0705
		1991/0706
		1991/0710
		1991/0711
		1991/0715
		1991/0716
		1991/0717
		1991/0718
		1991/0719
		1991/0720
		1991/0731
		1991/0806
		1991/0807
		1991/0809
		1991/0821
		1991/0904
		1991/0906
		1991/0912
		1991/0913
		1991/1211
		1991/1214
		1992/0323
		1992/0425
		1992/0728
		1992/0805
		1992/0806
		1992/0911		Add ins and outs
		1992/0917		Rename ins and outs to insl and outsl; add single-word ins and outs.
		1992/0922		Bug fix: wrong size instruction used in ins and outs.
		1992/1107		Add l0update.
		1992/1108		Add l1update. Rename cswizzle.
		1992/1109		XXX vga crap.
		1992/1110		Use different registers. (XXX why?)
		1992/1111		XXX more vga crap
		1992/1112		Bug fix: offset in MOVB. Comment fix.
		1992/1115		Rename bitrevtab.
		1992/1118		Change l0update, l1update, l2update argument order to match memmove.
		1992/1119		Change l0update to operate on 16 bits at a time.
		1992/1121		Bug fix: only LOOP once, so CX decrements only once.
		1992/1211		Add insb and outsb.
		1993/0212		Add dp8390inb and dp8390outb - delays for DP8390 ethernet.
		1993/0224		Bug fix?: handle intr 32 as 32 not 16.
		1993/0915		Import from Plan 9 to Brazil.
		1993/1027		Brazilism: u becomes up.
		1993/1113		Add forkret. Comment out l0update, l1update, l2update.
		1993/1116		Uncomment l0update, l1update, l2update.
		1993/1221		Remove l0update. Rename l1revsep, l2revsep to l1septab, l2septab. Update comments.
		1993/1229		Add l0update, this time without a table.
		1994/0130		Replace dp8390inb, dp8390outb with slowinb, slowoutb.
		1994/0201		Slow slowinb and slowoutb more.
		1994/0202		Replace slowinb, slowoutb implementations with old dp8390inb, dp8390outb.
		1994/0227		Set WP bit in CR0 to enforce write protection.
		1994/0302		Turn off CD, NW bits in CR0 - enable cache, enable write-through.
		1994/0409		Add Pentium-detection to x86. Add damove — forward-only memcpy.
		1994/0412		Syntax fix for is486 label. Remove l0update, l1update, l2update.
		1994/0602		Add fwblock and frblock — fiber block copy routines.
		1994/0603		Do not clear AX before inl (Why? speed fix or bug fix?). Remove idle.
		1994/0607		Bug fix x3: register, label mistakes in frblock and fwblock.
		1994/0610		Bug fix?: change processor detection to try to change reserved bits instead of setting them.
		1994/0622		Add getcr3.
		1994/0716		Bug fix?: cpu detection to handle 486s with CPUID. Add aamloop.
		1994/1029		Save CPUID into cpuid[ad]x. Add intr17, intr18.
		1994/1031		Rename x86 to x86cpuid; change to return CPUID (synthesized on old machines).
		1994/1101		Bug fix x2: return results instead of overwriting arguments, and restore original flags.
		1994/1114		Add xchgw.
		1995/0426		Comment CR0 bits.
		1995/0822		Save PC of splhi caller in m->splpc.
		1997/0327		XXX big rewrite
		1997/1101		XXX startup bits. Add _splx. Rename strayintr to _strayintr.
		1998/0130		Comment edit.
		1998/0401		Change rdmsr, wrmsr to use vlong instead of ulong pair.
		1998/0430		Comment edit - spelling.
		1998/0603		Comment edit - spelling.
		1998/0605		Bug fix? or paranoia: turn on interrupts before halting processor.
		1998/0606		Rename _splx to splxpc.
		1998/0916		Remove WAIT from fpsave. XXX Why?
		1999/0528		Use RDMSR 0x10 to time-stamp interrupts.
		1999/0609		Remove time stamps.
		1999/1008		Bug fix?: different implementation of FPOFF and FPON. XXX
		1999/1020		Bug fix?: incorrect DS possibly used during trap type code.
		2000/0929		XXX more FP crap.
		2000/1221		Add HLT (which was already mostly there as idle).
		2001/0527		Bug fix: one final check for ready processes before halting.
		2001/1130		Bug fix?: add proper RDTSC for VMware instead of using RDMSR 0x10.
		2002/0109		XXX more MMU crap
		2002/0413		Add sfence. Add swaplabel for debugging.
		2002/0703		Remove swaplabel.
		2003/0401		Formatting edit in #define DELAY. Add realmode.
		2003/0402		Remove realmode.